Re: [Qemu-devel] [PATCH 00/28] target-ppc: Altivec 2.07

[Richard W.M. Jones]

Tom,

I tested your patches [see below] and I found they work very well.
They solve all the immediate problems that libguestfs was hitting with
qemu not emulating certain POWER7 instructions.

I am now running a full libguestfs test which will take several hours,
but it looks as if -- even if this test fails -- it won't be because
of lack of emulation / missing instructions in qemu.

Thanks,
Rich.


1258017 (HEAD, master) target-ppc: Fix xxpermdi When T==A or T==B
a5a770e target-ppc: Altivec 2.07: Vector Permute and Exclusive OR
d2235b6 target-ppc: Altivec 2.07: Vector SHA Sigma Instructions
823d8bc target-ppc: Altivec 2.07: AES Instructions
de692f8 target-ppc: Altivec 2.07: Binary Coded Decimal Instructions
e57670e target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum
7aa4e18 target-ppc: Altivec 2.07: Vector Gather Bits by Bytes
0407211 target-ppc: Altivec 2.07: Doubleword Compares
fa643cd target-ppc: Altivec 2.07: vbpermq Instruction
3eefbc5 target-ppc: Altivec 2.07: Quadword Addition and Subtracation
679b19f target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift 
Instructions
c33fb5a target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates 
and Shifts
0d0e6fc target-ppc: Altivec 2.07: Vector Merge Instructions
535ddb7 target-ppc: Altivec 2.07: Unpack Signed Word Instructions
7c25020 target-ppc: Altivec 2.07: Pack Doubleword Instructions
1bfa3da target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions
46b62bf target-ppc: Altivec 2.07: Vector Population Count Instructions
1208e47 target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes
7560038 target-ppc: Altivec 2.07: vmuluw Instruction
5219437 target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions
e6d9b50 target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers
b00c954 target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword Modulo
59bae01 target-ppc: Altivec 2.07: Vector Logical Instructions
652fb6b target-ppc: Altivec 2.07: Add Support for R-Form Dual Instructions
1278f7d target-ppc: Altivec 2.07: Add Opcode Macro for VX Form Instructions
96645c6 target-ppc: Altivec 2.07: Add Support for Dual Altivec Instructions
c7dc903 target-ppc: Altivec 2.07: Add GEN_VXFORM3
cc356ef target-ppc: Altivec 2.07: Update AVR Structure
236fce3 target-ppc: Altivec 2.07: Add Instruction Flag
1963af7 target-ppc: Add Store Quadword Conditional
f74301d target-ppc: Add Load Quadword and Reserve
755065e target-ppc: Store Quadword
b278fa5 target-ppc: Load Quadword
aae0775 target-ppc: Add is_user_mode Utility Routine
702c075 target-ppc: Add Flag for ISA 2.07 Load/Store Quadword Instructions
c103fc8 target-ppc: Add bctar Instruction
cab1f12 target-ppc: Add Target Address SPR (TAR) to Power8
b904000 target-ppc: Add Flag for bctar
e1adfb7 target-ppc: Add ISA2.06 lfiwzx Instruction
ef84f63 target-ppc: Enable frsqrtes on Power7 and Power8
cfc3d6c target-ppc: Add ISA 2.06 ftsqrt
003634e target-ppc: Add ISA 2.06 ftdiv Instruction
8e28300 target-ppc: Add Flag for Power ISA V2.06 Floating Point Test 
Instructions
795d567 target-ppc: Fix and enable fri[mnpz]
7d69a6f target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
18f088a target-ppc: Add ISA2.06 Float to Integer Instructions
6211a33 target-ppc: Add Flag for ISA V2.06 Floating Point Conversion
bb961d5 target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
42cb1ee target-ppc: Add ISA2.06 lbarx, lharx Instructions
3ee50eb target-ppc: Add Flag for ISA2.06 Atomic Instructions
a38a0de target-ppc: Add ISA 2.06 divwe[o] Instructions
0964b12 target-ppc: Add ISA 2.06 divweu[o] Instructions
57c8cb1 target-ppc: Add ISA2.06 divde[o] Instructions
e711f0f target-ppc: Add ISA2.06 divdeu[o] Instructions
4360fcf target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
3813bf9 target-ppc: Add ISA2.06 bpermd Instruction
07cafd8 target-ppc: Scalar Non-Signalling Conversions
e3b40b5 target-ppc: Scalar Round to Single Precision
622d9fc target-ppc: Floating Merge Word Instructions
aab0146 target-ppc: Move To/From VSR Instructions
f716b79 target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc
613656c target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp
a80fde4 target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds
0ce9239 target-ppc: VSX Stage 4: add xsrsqrtesp
32dc58c target-ppc: VSX Stage 4: Add xssqrtsp
71b162a target-ppc: VSX Stage 4: Add xsresp
78a46d8 target-ppc: VSX Stage 4: Add xsdivsp
1c71eda target-ppc: VSX Stage 4: Add xsmulsp
c4ddfce target-ppc: VSX Stage 4: Add xsaddsp and xssubsp
76bec27 target-ppc: VSX Stage 4: Add stxsiwx and stxsspx
68de7cb target-ppc: VSX Stage 4: Refactor stxsdx
151f526 target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx
bdfbd58 target-ppc: VSX Stage 4: Refactor lxsdx
a918cda target-ppc: VSX Stage 4: Add VSX 2.07 Flag
18bf3f4 target-ppc: Add VSX Rounding Instructions
586ceee target-ppc: Add VSX ISA2.06 Integer Conversion Instructions
88d8f61 target-ppc: Add VSX Floating Point to Floating Point Conversion 
Instructions
3cd430d target-ppc: Add VSX Vector Compare Instructions
cb31645 target-ppc: Add VSX xmax/xmin Instructions
db495f4 target-ppc: Add VSX xscmp*dp Instructions
82f6825 target-ppc: Add VSX ISA2.06 Multiply Add Instructions
62cb1d9 target-ppc: Add VSX ISA2.06 xtsqrt Instructions
c5a492b target-ppc: Add VSX ISA2.06 xtdiv Instructions
8b06bc2 target-ppc: Add VSX ISA2.06 xrsqrte Instructions
a11ab0a target-ppc: Add VSX ISA2.06 xsqrt Instructions
41e6d0f target-ppc: Add VSX ISA2.06 xre Instructions
a8cead9 target-ppc: Add VSX ISA2.06 xdiv Instructions
6c6b83b target-ppc: Add VSX ISA2.06 xmul Instructions
7b2c1ef target-ppc: Add VSX ISA2.06 xadd/xsub Instructions
c69e231 target-ppc: General Support for VSX Helpers
a0d8089 target-ppc: Add set_fprf Argument to fload_invalid_op_excp()
46eef33 (origin/master, origin/HEAD) Fix QEMU build on OpenBSD on x86 archs


-- 
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
libguestfs lets you edit virtual machines.  Supports shell scripting,
bindings from many languages.  http://libguestfs.org