[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 22/30] target-arm: Remove failure status return from
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/30] target-arm: Remove failure status return from read/write_raw_cp_reg |
Date: |
Thu, 20 Feb 2014 11:17:26 +0000 |
The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns void and the
read function returns the value read, which in turn lets us
simplify the callers.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/helper.c | 36 ++++++++++++------------------------
1 file changed, 12 insertions(+), 24 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index f04e15e..59db883 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -126,35 +126,30 @@ static void raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
-static bool read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
- uint64_t *v)
+static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
{
- /* Raw read of a coprocessor register (as needed for migration, etc)
- * return true on success, false if the read is impossible for some reason.
- */
+ /* Raw read of a coprocessor register (as needed for migration, etc). */
if (ri->type & ARM_CP_CONST) {
- *v = ri->resetvalue;
+ return ri->resetvalue;
} else if (ri->raw_readfn) {
- *v = ri->raw_readfn(env, ri);
+ return ri->raw_readfn(env, ri);
} else if (ri->readfn) {
- *v = ri->readfn(env, ri);
+ return ri->readfn(env, ri);
} else {
- *v = raw_read(env, ri);
+ return raw_read(env, ri);
}
- return true;
}
-static bool write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
+static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
int64_t v)
{
/* Raw write of a coprocessor register (as needed for migration, etc).
- * Return true on success, false if the write is impossible for some
reason.
* Note that constant registers are treated as write-ignored; the
* caller should check for success by whether a readback gives the
* value written.
*/
if (ri->type & ARM_CP_CONST) {
- return true;
+ return;
} else if (ri->raw_writefn) {
ri->raw_writefn(env, ri, v);
} else if (ri->writefn) {
@@ -162,7 +157,6 @@ static bool write_raw_cp_reg(CPUARMState *env, const
ARMCPRegInfo *ri,
} else {
raw_write(env, ri, v);
}
- return true;
}
bool write_cpustate_to_list(ARMCPU *cpu)
@@ -174,7 +168,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
for (i = 0; i < cpu->cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
const ARMCPRegInfo *ri;
- uint64_t v;
+
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
if (!ri) {
ok = false;
@@ -183,11 +177,7 @@ bool write_cpustate_to_list(ARMCPU *cpu)
if (ri->type & ARM_CP_NO_MIGRATE) {
continue;
}
- if (!read_raw_cp_reg(&cpu->env, ri, &v)) {
- ok = false;
- continue;
- }
- cpu->cpreg_values[i] = v;
+ cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
}
return ok;
}
@@ -200,7 +190,6 @@ bool write_list_to_cpustate(ARMCPU *cpu)
for (i = 0; i < cpu->cpreg_array_len; i++) {
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
uint64_t v = cpu->cpreg_values[i];
- uint64_t readback;
const ARMCPRegInfo *ri;
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
@@ -215,9 +204,8 @@ bool write_list_to_cpustate(ARMCPU *cpu)
* (to catch read-only registers and partially read-only
* registers where the incoming migration value doesn't match)
*/
- if (!write_raw_cp_reg(&cpu->env, ri, v) ||
- !read_raw_cp_reg(&cpu->env, ri, &readback) ||
- readback != v) {
+ write_raw_cp_reg(&cpu->env, ri, v);
+ if (read_raw_cp_reg(&cpu->env, ri) != v) {
ok = false;
}
}
--
1.8.5
- [Qemu-devel] [PULL 16/30] target-arm: Split cpreg access checks out from read/write functions, (continued)
- [Qemu-devel] [PULL 16/30] target-arm: Split cpreg access checks out from read/write functions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 30/30] linux-user: AArch64: Fix exclusive store of the zero register, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 29/30] target-arm: A64: Implement unprivileged load/store, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 28/30] target-arm: A64: Implement narrowing three-reg-diff operations, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 27/30] target-arm: A64: Implement the wide 3-reg-different operations, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 07/30] target-arm: A64: Implement floating point pairwise insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 26/30] target-arm: A64: Add most remaining three-reg-diff widening ops, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 25/30] target-arm: A64: Add opcode comments to disas_simd_three_reg_diff, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 24/30] target-arm: A64: Implement store-exclusive for system mode, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 23/30] target-arm: Fix incorrect type for value argument to write_raw_cp_reg, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 22/30] target-arm: Remove failure status return from read/write_raw_cp_reg,
Peter Maydell <=
- [Qemu-devel] [PULL 20/30] target-arm: Drop success/fail return from cpreg read and write functions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 21/30] target-arm: Remove unnecessary code now read/write fns can't fail, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 19/30] target-arm: Convert miscellaneous reginfo structs to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 08/30] softfloat: Support halving the result of muladd operation, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 04/30] target-arm: A64: Implement SIMD scalar indexed instructions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 02/30] target-arm: A64: Implement plain vector SIMD indexed element insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 14/30] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 17/30] target-arm: Convert performance monitor reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 15/30] target-arm: Stop underdecoding ARM946 PRBS registers, Peter Maydell, 2014/02/20