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[Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr subst
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr substruct |
Date: |
Thu, 20 Feb 2014 11:17:17 +0000 |
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu.h | 5 -----
1 file changed, 5 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 52894fc..ab57f55 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -217,11 +217,6 @@ typedef struct CPUARMState {
uint32_t c15_power_control; /* power control */
} cp15;
- /* System registers (AArch64) */
- struct {
- uint64_t tpidr_el0;
- } sr;
-
struct {
uint32_t other_sp;
uint32_t vecbase;
--
1.8.5
- [Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure, (continued)
- [Qemu-devel] [PULL 01/30] hw/intc/arm_gic: Fix NVIC assertion failure, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 04/30] target-arm: A64: Implement SIMD scalar indexed instructions, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 02/30] target-arm: A64: Implement plain vector SIMD indexed element insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 14/30] target-arm: Log bad system register accesses with LOG_UNIMP, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 17/30] target-arm: Convert performance monitor reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 15/30] target-arm: Stop underdecoding ARM946 PRBS registers, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 12/30] target-arm: Restrict check_ap() use of S and R bits to v6 and earlier, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 18/30] target-arm: Convert generic timer reginfo to accessfn, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 11/30] target-arm: Define names for SCTLR bits, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 03/30] target-arm: A64: Implement long vector x indexed insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 13/30] target-arm: Remove unused ARMCPUState sr substruct,
Peter Maydell <=
- [Qemu-devel] [PULL 06/30] target-arm: A64: Implement SIMD FP compare and set insns, Peter Maydell, 2014/02/20
- [Qemu-devel] [PULL 05/30] target-arm: A64: Implement scalar three different instructions, Peter Maydell, 2014/02/20
- Re: [Qemu-devel] [PULL 00/30] target-arm queue, Peter Maydell, 2014/02/21