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[Qemu-devel] [PATCH 26/51] pc: map PCI address space as catchall region
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 26/51] pc: map PCI address space as catchall region for not mapped addresses |
Date: |
Fri, 21 Feb 2014 02:17:02 -0600 |
From: "Michael S. Tsirkin" <address@hidden>
With a help of negative memory region priority PCI address space
is mapped underneath RAM regions effectively catching every access
to addresses not mapped by any other region.
It simplifies PCI address space mapping into system address space.
Signed-off-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Igor Mammedov <address@hidden>
(cherry picked from commit 83d08f2673504a299194dcac1657a13754b5932a)
*prereq for ddaaefb backport
Signed-off-by: Michael Roth <address@hidden>
---
hw/i386/pc.c | 20 ++++++--------------
hw/i386/pc_piix.c | 2 --
hw/pci-host/piix.c | 26 ++++----------------------
hw/pci-host/q35.c | 27 +++++----------------------
include/hw/i386/pc.h | 14 ++------------
include/hw/pci-host/q35.h | 2 --
6 files changed, 17 insertions(+), 74 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 12c436e..6c82ada 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1093,21 +1093,13 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
below_4g_mem_size,
return guest_info;
}
-void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
- uint64_t pci_hole64_size)
+/* setup pci memory address space mapping into system address space */
+void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
+ MemoryRegion *pci_address_space)
{
- if ((sizeof(hwaddr) == 4) || (!pci_hole64_size)) {
- return;
- }
- /*
- * BIOS does not set MTRR entries for the 64 bit window, so no need to
- * align address to power of two. Align address at 1G, this makes sure
- * it can be exactly covered with a PAT entry even when using huge
- * pages.
- */
- pci_info->w64.begin = ROUND_UP(pci_hole64_start, 0x1ULL << 30);
- pci_info->w64.end = pci_info->w64.begin + pci_hole64_size;
- assert(pci_info->w64.begin <= pci_info->w64.end);
+ /* Set to lower priority than RAM */
+ memory_region_add_subregion_overlap(system_memory, 0x0,
+ pci_address_space, -1);
}
void pc_acpi_init(const char *default_dsdt)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 2111f01..29b47d4 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -149,8 +149,6 @@ static void pc_init1(QEMUMachineInitArgs *args,
if (pci_enabled) {
pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, &isa_bus, gsi,
system_memory, system_io, args->ram_size,
- below_4g_mem_size,
- 0x100000000ULL - below_4g_mem_size,
above_4g_mem_size,
pci_memory, ram_memory);
} else {
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index edc974e..63be7f6 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -103,8 +103,6 @@ struct PCII440FXState {
MemoryRegion *system_memory;
MemoryRegion *pci_address_space;
MemoryRegion *ram_memory;
- MemoryRegion pci_hole;
- MemoryRegion pci_hole_64bit;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
uint8_t smm_enabled;
@@ -313,8 +311,6 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- hwaddr pci_hole_start,
- hwaddr pci_hole_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *pci_address_space,
MemoryRegion *ram_memory)
@@ -327,7 +323,6 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
PCII440FXState *f;
unsigned i;
I440FXState *i440fx;
- uint64_t pci_hole64_size;
dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
s = PCI_HOST_BRIDGE(dev);
@@ -355,23 +350,10 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
i440fx->pci_info.w32.begin = 0xe0000000;
}
- memory_region_init_alias(&f->pci_hole, OBJECT(d), "pci-hole",
f->pci_address_space,
- pci_hole_start, pci_hole_size);
- memory_region_add_subregion(f->system_memory, pci_hole_start,
&f->pci_hole);
-
- pci_hole64_size = pci_host_get_hole64_size(i440fx->pci_hole64_size);
-
- pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
- pci_hole64_size);
- memory_region_init_alias(&f->pci_hole_64bit, OBJECT(d), "pci-hole64",
- f->pci_address_space,
- i440fx->pci_info.w64.begin,
- pci_hole64_size);
- if (pci_hole64_size) {
- memory_region_add_subregion(f->system_memory,
- i440fx->pci_info.w64.begin,
- &f->pci_hole_64bit);
- }
+ /* setup pci memory mapping */
+ pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
+ f->pci_address_space);
+
memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
f->pci_address_space, 0xa0000, 0x20000);
memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
index c043998..81c8240 100644
--- a/hw/pci-host/q35.c
+++ b/hw/pci-host/q35.c
@@ -356,28 +356,11 @@ static int mch_init(PCIDevice *d)
{
int i;
MCHPCIState *mch = MCH_PCI_DEVICE(d);
- uint64_t pci_hole64_size;
-
- /* setup pci memory regions */
- memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole",
- mch->pci_address_space,
- mch->below_4g_mem_size,
- 0x100000000ULL - mch->below_4g_mem_size);
- memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
- &mch->pci_hole);
-
- pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size);
- pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
- pci_hole64_size);
- memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64",
- mch->pci_address_space,
- mch->pci_info.w64.begin,
- pci_hole64_size);
- if (pci_hole64_size) {
- memory_region_add_subregion(mch->system_memory,
- mch->pci_info.w64.begin,
- &mch->pci_hole_64bit);
- }
+
+ /* setup pci memory mapping */
+ pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory,
+ mch->pci_address_space);
+
/* smram */
cpu_smm_register(&mch_set_smm, mch);
memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region",
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 09652fb..8ea1a98 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -128,17 +128,9 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t
below_4g_mem_size,
#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
#define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
-static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size)
-{
- if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) {
- return 1ULL << 62;
- } else {
- return pci_hole64_size;
- }
-}
-void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
- uint64_t pci_hole64_size);
+void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
+ MemoryRegion *pci_address_space);
FWCfgState *pc_memory_init(MemoryRegion *system_memory,
const char *kernel_filename,
@@ -187,8 +179,6 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int
*piix_devfn,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
- hwaddr pci_hole_start,
- hwaddr pci_hole_size,
ram_addr_t above_4g_mem_size,
MemoryRegion *pci_memory,
MemoryRegion *ram_memory);
diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
index 309065f..d0355b7 100644
--- a/include/hw/pci-host/q35.h
+++ b/include/hw/pci-host/q35.h
@@ -53,8 +53,6 @@ typedef struct MCHPCIState {
MemoryRegion *address_space_io;
PAMMemoryRegion pam_regions[13];
MemoryRegion smram_region;
- MemoryRegion pci_hole;
- MemoryRegion pci_hole_64bit;
PcPciInfo pci_info;
uint8_t smm_enabled;
ram_addr_t below_4g_mem_size;
--
1.7.9.5
- [Qemu-devel] [PATCH 15/51] intel-hda: fix position buffer, (continued)
- [Qemu-devel] [PATCH 15/51] intel-hda: fix position buffer, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 19/51] vl: add missing transition debug->finish_migrate, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 18/51] migration: Fix rate limit, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 20/51] x86: only allow real mode to access 32bit without LMA, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 21/51] qdev-monitor: Avoid device_add crashing on non-device driver name, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 22/51] split definitions for exec.c and translate-all.c radix trees, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 06/51] virtio-blk: switch exit callback to VirtioDeviceClass, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 24/51] exec: pass hw address to phys_page_find, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 23/51] exec: replace leaf with skip, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 25/51] exec: separate sections and nodes per address space, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 26/51] pc: map PCI address space as catchall region for not mapped addresses,
Michael Roth <=
- [Qemu-devel] [PATCH 28/51] target-mips: fix 64-bit FPU config for user-mode emulation, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 29/51] linux-user: pass correct parameter to do_shmctl(), Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 30/51] linux-user: create target_structs header to place ipc_perm and shmid_ds, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 27/51] piix: fix 32bit pci hole, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 32/51] tcg/optimize: fix known-zero bits for right shift ops, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 31/51] Fix QEMU build on OpenBSD on x86 archs, Michael Roth, 2014/02/21
- [Qemu-devel] [PATCH 34/51] block/iscsi: use a bh to schedule co reentrance, Michael Roth, 2014/02/21