Re: [Qemu-devel] [PATCH v3 18/31] target-arm: Get MMU index information correct for A64 code

[Peter Crosthwaite]

On Sun, Feb 16, 2014 at 2:07 AM, Peter Maydell <address@hidden> wrote:
> Emit the correct MMU index information for loads and stores from
> A64 code, rather than hardwiring it to "always kernel mode",
> by storing the exception level in the TB flags, and make
> cpu_mmu_index() return the right answer when the CPU is in
> AArch64 mode.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

> ---
>  target-arm/cpu.h           | 11 ++++++++---
>  target-arm/translate-a64.c |  2 +-
>  2 files changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index db74ab7..ec0214d 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1057,7 +1057,7 @@ static inline CPUARMState *cpu_init(const char 
> *cpu_model)
>  #define MMU_USER_IDX 1
>  static inline int cpu_mmu_index (CPUARMState *env)
>  {
> -    return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
> +    return arm_current_pl(env) ? 0 : 1;
>  }
>
>  #include "exec/cpu-all.h"
> @@ -1084,7 +1084,9 @@ static inline int cpu_mmu_index (CPUARMState *env)
>  #define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
>  #define ARM_TBFLAG_BSWAP_CODE_MASK  (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
>
> -/* Bit usage when in AArch64 state: currently no bits defined */
> +/* Bit usage when in AArch64 state */
> +#define ARM_TBFLAG_AA64_EL_SHIFT    0
> +#define ARM_TBFLAG_AA64_EL_MASK     (0x3 << ARM_TBFLAG_AA64_EL_SHIFT)
>
>  /* some convenience accessor macros */
>  #define ARM_TBFLAG_AARCH64_STATE(F) \
> @@ -1103,13 +1105,16 @@ static inline int cpu_mmu_index (CPUARMState *env)
>      (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
>  #define ARM_TBFLAG_BSWAP_CODE(F) \
>      (((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
> +#define ARM_TBFLAG_AA64_EL(F) \
> +    (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
>
>  static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
>                                          target_ulong *cs_base, int *flags)
>  {
>      if (is_a64(env)) {
>          *pc = env->pc;
> -        *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
> +        *flags = ARM_TBFLAG_AARCH64_STATE_MASK
> +            | (arm_current_pl(env) << ARM_TBFLAG_AA64_EL_SHIFT);
>      } else {
>          int privmode;
>          *pc = env->regs[15];
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index 7c55a90..1714df2 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -8844,7 +8844,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
>      dc->condexec_mask = 0;
>      dc->condexec_cond = 0;
>  #if !defined(CONFIG_USER_ONLY)
> -    dc->user = 0;
> +    dc->user = (ARM_TBFLAG_AA64_EL(tb->flags) == 0);
>  #endif
>      dc->vfp_enabled = 0;
>      dc->vec_len = 0;
> --
> 1.8.5
>
>