Re: [Qemu-devel] [PATCH v3 01/31] target-arm: Fix raw read and write functions on AArch64 registers

[Peter Crosthwaite]

On Sun, Feb 16, 2014 at 2:06 AM, Peter Maydell <address@hidden> wrote:
> The raw read and write functions were using the ARM_CP_64BIT flag in
> ri->type to determine whether to treat the register's state field as
> uint32_t or uint64_t; however AArch64 register info structs don't use
> that flag. Abstract out the "how big is the field?" test into a
> function and fix it to work for AArch64 registers. For this to work
> we must ensure that the reginfo structs put into the hashtable have
> the correct state field for their use, not the placeholder STATE_BOTH.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

> ---
>  target-arm/cpu.c    | 2 +-
>  target-arm/cpu.h    | 8 ++++++++
>  target-arm/helper.c | 8 ++++++--
>  3 files changed, 15 insertions(+), 3 deletions(-)
>
> diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> index 6e7ce89..fe18b65 100644
> --- a/target-arm/cpu.c
> +++ b/target-arm/cpu.c
> @@ -60,7 +60,7 @@ static void cp_reg_reset(gpointer key, gpointer value, 
> gpointer opaque)
>          return;
>      }
>
> -    if (ri->type & ARM_CP_64BIT) {
> +    if (cpreg_field_is_64bit(ri)) {
>          CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
>      } else {
>          CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 3c8a2db..4473fad 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -959,6 +959,14 @@ uint64_t arm_cp_read_zero(CPUARMState *env, const 
> ARMCPRegInfo *ri);
>   */
>  void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque);
>
> +/* Return true if this reginfo struct's field in the cpu state struct
> + * is 64 bits wide.
> + */
> +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri)
> +{
> +    return (ri->state == ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BIT);
> +}
> +
>  static inline bool cp_access_ok(int current_pl,
>                                  const ARMCPRegInfo *ri, int isread)
>  {
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index b547f04..1ecc55e 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -109,7 +109,7 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, 
> uint8_t *buf, int reg)
>
>  static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
>  {
> -    if (ri->type & ARM_CP_64BIT) {
> +    if (cpreg_field_is_64bit(ri)) {
>          return CPREG_FIELD64(env, ri);
>      } else {
>          return CPREG_FIELD32(env, ri);
> @@ -119,7 +119,7 @@ static uint64_t raw_read(CPUARMState *env, const 
> ARMCPRegInfo *ri)
>  static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
>                        uint64_t value)
>  {
> -    if (ri->type & ARM_CP_64BIT) {
> +    if (cpreg_field_is_64bit(ri)) {
>          CPREG_FIELD64(env, ri) = value;
>      } else {
>          CPREG_FIELD32(env, ri) = value;
> @@ -1962,6 +1962,10 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const 
> ARMCPRegInfo *r,
>      if (opaque) {
>          r2->opaque = opaque;
>      }
> +    /* reginfo passed to helpers is correct for the actual access,
> +     * and is never ARM_CP_STATE_BOTH:
> +     */
> +    r2->state = state;
>      /* Make sure reginfo passed to helpers for wildcarded regs
>       * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
>       */
> --
> 1.8.5
>
>