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[Qemu-devel] [PULL 19/45] target-arm: Implement AArch64 TLB invalidate o
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 19/45] target-arm: Implement AArch64 TLB invalidate ops |
Date: |
Wed, 26 Feb 2014 18:02:09 +0000 |
Implement the AArch64 TLB invalidate operations. This is
the full set of TLBI ops defined for a CPU which doesn't
implement EL2 or EL3.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index bc6720e..13a55a5 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1525,6 +1525,30 @@ static CPAccessResult aa64_cacheop_access(CPUARMState
*env,
return CP_ACCESS_OK;
}
+static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate by VA (AArch64 version) */
+ uint64_t pageaddr = value << 12;
+ tlb_flush_page(env, pageaddr);
+}
+
+static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate by VA, all ASIDs (AArch64 version) */
+ uint64_t pageaddr = value << 12;
+ tlb_flush_page(env, pageaddr);
+}
+
+static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ /* Invalidate by ASID (AArch64 version) */
+ int asid = extract64(value, 48, 16);
+ tlb_flush(env, asid == 0);
+}
+
static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
@@ -1583,6 +1607,55 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
.opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
.access = PL1_W, .type = ARM_CP_NOP },
+ /* TLBI operations */
+ { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbiall_write },
+ { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_va_write },
+ { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_asid_write },
+ { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_vaa_write },
+ { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_va_write },
+ { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_vaa_write },
+ { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbiall_write },
+ { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_va_write },
+ { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_asid_write },
+ { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_vaa_write },
+ { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_va_write },
+ { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
+ .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
+ .writefn = tlbi_aa64_vaa_write },
REGINFO_SENTINEL
};
--
1.9.0
- [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions, (continued)
- [Qemu-devel] [PULL 34/45] target-arm: A64: Implement MSR (immediate) instructions, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 15/45] target-arm: A64: Make cache ID registers visible to AArch64, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 05/45] hw/intc/exynos4210_combiner: Don't overrun output_irq array in init, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 20/45] target-arm: Implement AArch64 dummy MDSCR_EL1, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 14/45] target-arm: Fix raw read and write functions on AArch64 registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 13/45] hw: arm_gic_kvm: Add KVM VGIC save/restore logic, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 28/45] target-arm: Implement AArch64 ID and feature registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 26/45] target-arm: Implement AArch64 MPIDR, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 08/45] hw/intc/arm_gic: Fix GIC_SET_LEVEL, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 32/45] target-arm: A64: Implement WFI, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 19/45] target-arm: Implement AArch64 TLB invalidate ops,
Peter Maydell <=
- [Qemu-devel] [PULL 02/45] hw/net/stellaris_enet: Avoid unintended sign extension, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 01/45] hw/misc/arm_sysctl: Fix bad boundary check on mb clock accesses, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 09/45] linux-headers: Update from v3.14-rc3, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 21/45] target-arm: Implement AArch64 memory attribute registers, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 18/45] target-arm: Implement AArch64 cache invalidate/clean ops, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 03/45] hw/timer/arm_timer: Avoid array overrun for bad addresses, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 07/45] target-arm: Load correct access bits from ARMv5 level 2 page table descriptors, Peter Maydell, 2014/02/26
- [Qemu-devel] [PULL 06/45] hw/arm/musicpal: Remove nonexistent CDTP2, CDTP3 registers, Peter Maydell, 2014/02/26
- Re: [Qemu-devel] [PULL 00/45] target-arm queue, Peter Maydell, 2014/02/27