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[Qemu-devel] [PATCH 4/4] target-ppc: MSR_POW not supported on POWER7/7+/
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From: |
Anton Blanchard |
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Subject: |
[Qemu-devel] [PATCH 4/4] target-ppc: MSR_POW not supported on POWER7/7+/8 |
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Date: |
Thu, 6 Mar 2014 15:51:49 +1100 |
Remove MSR_POW from the msr_mask for POWER7/7+/8.
Signed-off-by: Anton Blanchard <address@hidden>
---
Index: b/target-ppc/translate_init.c
===================================================================
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7074,7 +7074,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc,
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206;
- pcc->msr_mask = 0x800000000284FF37ULL;
+ pcc->msr_mask = 0x800000000280FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7117,7 +7117,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc,
PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206;
- pcc->msr_mask = 0x800000000284FF37ULL;
+ pcc->msr_mask = 0x800000000280FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
@@ -7173,7 +7173,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc,
PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207;
- pcc->msr_mask = 0x800000000284FF37ULL;
+ pcc->msr_mask = 0x800000000280FF37ULL;
pcc->mmu_model = POWERPC_MMU_2_06;
#if defined(CONFIG_SOFTMMU)
pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;