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[Qemu-devel] [PULL 108/130] target-ppc: Altivec 2.07: Change Bit Masks t
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 108/130] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts |
Date: |
Fri, 7 Mar 2014 00:33:55 +0100 |
From: Tom Musta <address@hidden>
Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and
shift
helpers uses a formula to compute a bit mask used to extract the rotate/shift
amount from the VRB register. What is desired is:
mask = (1 << (3 + log2(sizeof(element)))) - 1
but what is implemented is:
mask = (1 << (3 + (sizeof(element)/2))) - 1
This produces correct answers when "element" is uint8_t, uint16_t or uint_32t.
But
it breaks down when element is uint64_t.
This patch corrects the situation. Since the mask is known at compile time, the
macros are changed to simply accept the mask as an argument.
Subsequent patches in this series will add double-word variants of rotates and
shifts and thus take advantage of this fix.
Signed-off-by: Tom Musta <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/int_helper.c | 40 +++++++++++++++-------------------------
1 file changed, 15 insertions(+), 25 deletions(-)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 56e8d9a..59b5a1f 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1128,23 +1128,20 @@ VRFI(p, float_round_up)
VRFI(z, float_round_to_zero)
#undef VRFI
-#define VROTATE(suffix, element) \
+#define VROTATE(suffix, element, mask) \
void helper_vrl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- unsigned int mask = ((1 << \
- (3 + (sizeof(a->element[0]) >> 1))) \
- - 1); \
unsigned int shift = b->element[i] & mask; \
r->element[i] = (a->element[i] << shift) | \
(a->element[i] >> (sizeof(a->element[0]) * 8 - shift)); \
} \
}
-VROTATE(b, u8)
-VROTATE(h, u16)
-VROTATE(w, u32)
+VROTATE(b, u8, 0x7)
+VROTATE(h, u16, 0xF)
+VROTATE(w, u32, 0x1F)
#undef VROTATE
void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
@@ -1225,23 +1222,20 @@ VSHIFT(r, RIGHT)
#undef LEFT
#undef RIGHT
-#define VSL(suffix, element) \
+#define VSL(suffix, element, mask) \
void helper_vsl##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- unsigned int mask = ((1 << \
- (3 + (sizeof(a->element[0]) >> 1))) \
- - 1); \
unsigned int shift = b->element[i] & mask; \
\
r->element[i] = a->element[i] << shift; \
} \
}
-VSL(b, u8)
-VSL(h, u16)
-VSL(w, u32)
+VSL(b, u8, 0x7)
+VSL(h, u16, 0x0F)
+VSL(w, u32, 0x1F)
#undef VSL
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
@@ -1325,26 +1319,22 @@ VSPLTI(h, s16, int16_t)
VSPLTI(w, s32, int32_t)
#undef VSPLTI
-#define VSR(suffix, element) \
+#define VSR(suffix, element, mask) \
void helper_vsr##suffix(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- unsigned int mask = ((1 << \
- (3 + (sizeof(a->element[0]) >> 1))) \
- - 1); \
unsigned int shift = b->element[i] & mask; \
- \
r->element[i] = a->element[i] >> shift; \
} \
}
-VSR(ab, s8)
-VSR(ah, s16)
-VSR(aw, s32)
-VSR(b, u8)
-VSR(h, u16)
-VSR(w, u32)
+VSR(ab, s8, 0x7)
+VSR(ah, s16, 0xF)
+VSR(aw, s32, 0x1F)
+VSR(b, u8, 0x7)
+VSR(h, u16, 0xF)
+VSR(w, u32, 0x1F)
#undef VSR
void helper_vsro(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
--
1.8.1.4
- [Qemu-devel] [PULL 101/130] target-ppc: Altivec 2.07: vmuluw Instruction, (continued)
- [Qemu-devel] [PULL 101/130] target-ppc: Altivec 2.07: vmuluw Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 104/130] target-ppc: Altivec 2.07: Vector Min/Max Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 100/130] target-ppc: Altivec 2.07: Multiply Even/Odd Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 099/130] target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit Integers, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 106/130] target-ppc: Altivec 2.07: Unpack Signed Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 102/130] target-ppc: Altivec 2.07: Add Vector Count Leading Zeroes, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 103/130] target-ppc: Altivec 2.07: Vector Population Count Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 107/130] target-ppc: Altivec 2.07: Vector Merge Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 109/130] target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 105/130] target-ppc: Altivec 2.07: Pack Doubleword Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 108/130] target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and Shifts,
Alexander Graf <=
- [Qemu-devel] [PULL 110/130] target-ppc: Altivec 2.07: Quadword Addition and Subtracation, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 111/130] target-ppc: Altivec 2.07: vbpermq Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 112/130] target-ppc: Altivec 2.07: Doubleword Compares, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 120/130] target-ppc/translate.c: Use ULL suffix for 64 bit constants, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 114/130] target-ppc: Altivec 2.07: Vector Polynomial Multiply Sum, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 118/130] target-ppc: Altivec 2.07: Vector Permute and Exclusive OR, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 119/130] spapr-vlan: flush queue whenever can_receive can go from false to true, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 115/130] target-ppc: Altivec 2.07: Binary Coded Decimal Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 117/130] target-ppc: Altivec 2.07: Vector SHA Sigma Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 113/130] target-ppc: Altivec 2.07: Vector Gather Bits by Bytes, Alexander Graf, 2014/03/06