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[Qemu-devel] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and x
From: |
Alexander Graf |
Subject: |
[Qemu-devel] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp |
Date: |
Fri, 7 Mar 2014 00:32:53 +0100 |
From: Tom Musta <address@hidden>
This patch adds the VSX Scalar Convert Unsigned Integer Doubleword
to Floating Point Format and Round to Single Precision (xscvuxdsp)
and VSX Scalar Convert Signed Integer Douglbeword to Floating Point
Format and Round to Single Precision (xscvsxdsp) instructions.
The existing integer to floating point conversion macro (VSX_CVT_INT_TO_FP)
is modified to support the rounding of the intermediate floating point
result to single precision.
Signed-off-by: Tom Musta <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Alexander Graf <address@hidden>
---
target-ppc/fpu_helper.c | 27 ++++++++++++++++-----------
target-ppc/helper.h | 2 ++
target-ppc/translate.c | 4 ++++
3 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 7e5003a..1dfb3c0 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2558,7 +2558,7 @@ VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, f32[j],
u32[i], i, 0)
* jdef - definition of the j index (i or 2*i)
* sfprf - set FPRF
*/
-#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf) \
+#define VSX_CVT_INT_TO_FP(op, nels, stp, ttp, sfld, tfld, jdef, sfprf, r2sp) \
void helper_##op(CPUPPCState *env, uint32_t opcode) \
{ \
ppc_vsr_t xt, xb; \
@@ -2570,6 +2570,9 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
for (i = 0; i < nels; i++) { \
int j = jdef; \
xt.tfld = stp##_to_##ttp(xb.sfld, &env->fp_status); \
+ if (r2sp) { \
+ xt.tfld = helper_frsp(env, xt.tfld); \
+ } \
if (sfprf) { \
helper_compute_fprf(env, xt.tfld, sfprf); \
} \
@@ -2579,20 +2582,22 @@ void helper_##op(CPUPPCState *env, uint32_t opcode)
\
helper_float_check_status(env); \
}
-VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, u64[j], f64[i], i, 1)
-VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, u64[j], f64[i], i, 1)
-VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, u64[j], f64[i], i, 0)
-VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, u64[j], f64[i], i, 0)
+VSX_CVT_INT_TO_FP(xscvsxddp, 1, int64, float64, u64[j], f64[i], i, 1, 0)
+VSX_CVT_INT_TO_FP(xscvuxddp, 1, uint64, float64, u64[j], f64[i], i, 1, 0)
+VSX_CVT_INT_TO_FP(xscvsxdsp, 1, int64, float64, u64[j], f64[i], i, 1, 1)
+VSX_CVT_INT_TO_FP(xscvuxdsp, 1, uint64, float64, u64[j], f64[i], i, 1, 1)
+VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, u64[j], f64[i], i, 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, u64[j], f64[i], i, 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, u32[j], f64[i], \
- 2*i + JOFFSET, 0)
+ 2*i + JOFFSET, 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, u32[j], f64[i], \
- 2*i + JOFFSET, 0)
+ 2*i + JOFFSET, 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, u64[i], f32[j], \
- 2*i + JOFFSET, 0)
+ 2*i + JOFFSET, 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, u64[i], f32[j], \
- 2*i + JOFFSET, 0)
-VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0)
-VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0)
+ 2*i + JOFFSET, 0, 0)
+VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, u32[j], f32[i], i, 0, 0)
+VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, u32[j], f32[i], i, 0, 0)
/* For "use current rounding mode", define a value that will not be one of
* the existing rounding model enums.
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 655b670..6250eba 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -279,6 +279,8 @@ DEF_HELPER_2(xscvdpsxws, void, env, i32)
DEF_HELPER_2(xscvdpuxds, void, env, i32)
DEF_HELPER_2(xscvdpuxws, void, env, i32)
DEF_HELPER_2(xscvsxddp, void, env, i32)
+DEF_HELPER_2(xscvuxdsp, void, env, i32)
+DEF_HELPER_2(xscvsxdsp, void, env, i32)
DEF_HELPER_2(xscvuxddp, void, env, i32)
DEF_HELPER_2(xsrdpi, void, env, i32)
DEF_HELPER_2(xsrdpic, void, env, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b2a610c..61271e1 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7373,6 +7373,8 @@ GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
+GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
@@ -10195,6 +10197,8 @@ GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
+GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
+GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
--
1.8.1.4
- [Qemu-devel] [PULL 040/130] target-ppc: VSX Stage 4: Add xsmulsp, (continued)
- [Qemu-devel] [PULL 040/130] target-ppc: VSX Stage 4: Add xsmulsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 028/130] target-ppc: Add VSX xscmp*dp Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 042/130] target-ppc: VSX Stage 4: Add xsresp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 022/130] target-ppc: Add VSX ISA2.06 xre Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 045/130] target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 030/130] target-ppc: Add VSX Vector Compare Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 041/130] target-ppc: VSX Stage 4: Add xsdivsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 047/130] target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 049/130] target-ppc: Floating Merge Word Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 043/130] target-ppc: VSX Stage 4: Add xssqrtsp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 046/130] target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp,
Alexander Graf <=
- [Qemu-devel] [PULL 056/130] target-ppc: Add ISA 2.06 divweu[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 053/130] target-ppc: Add Flag for ISA2.06 Divide Extended Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 057/130] target-ppc: Add ISA 2.06 divwe[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 050/130] target-ppc: Scalar Round to Single Precision, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 048/130] target-ppc: Move To/From VSR Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 044/130] target-ppc: VSX Stage 4: add xsrsqrtesp, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 058/130] target-ppc: Add Flag for ISA2.06 Atomic Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 055/130] target-ppc: Add ISA2.06 divde[o] Instructions, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 052/130] target-ppc: Add ISA2.06 bpermd Instruction, Alexander Graf, 2014/03/06
- [Qemu-devel] [PULL 068/130] target-ppc: Enable frsqrtes on Power7 and Power8, Alexander Graf, 2014/03/06