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[Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm o
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes |
Date: |
Sun, 9 Mar 2014 15:11:03 +0000 |
Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 45f8996..8bf66a6 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s,
uint32_t insn)
handle_vec_simd_sqshrn(s, true, false, is_u, is_u,
immh, immb, opcode, rn, rd);
break;
- default:
+ case 0x8: /* SRI */
+ case 0xc: /* SQSHLU */
+ case 0xe: /* SQSHL, UQSHL */
+ case 0x1f: /* FCVTZS, FCVTZU */
unsupported_encoding(s, insn);
break;
+ default:
+ unallocated_encoding(s);
+ break;
}
}
@@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s,
uint32_t insn)
handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb,
opcode, rn, rd);
break;
+ case 0x8: /* SRI */
+ case 0xc: /* SQSHLU */
+ case 0xe: /* SQSHL, UQSHL */
case 0x1f: /* FCVTZS/ FCVTZU */
unsupported_encoding(s, insn);
return;
default:
- unsupported_encoding(s, insn);
+ unallocated_encoding(s);
return;
}
}
--
1.9.0
- [Qemu-devel] [PATCH 00/16] A64 Neon patches: sixth set, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 12/16] target-arm: A64: List unsupported shift-imm opcodes,
Peter Maydell <=
- [Qemu-devel] [PATCH 10/16] target-arm: A64: Implement FCVTN, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 11/16] target-arm: A64: Implement FCVTL, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 02/16] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 04/16] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 07/16] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 08/16] target-arm: A64: Implement SHLL, SHLL2, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 09/16] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/09
- [Qemu-devel] [PATCH 13/16] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/09