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[Qemu-devel] [PATCH v2 25/25] scripts/qemu-binfmt-conf.sh: Add AArch64 r
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 25/25] scripts/qemu-binfmt-conf.sh: Add AArch64 registration |
Date: |
Fri, 14 Mar 2014 18:38:14 +0000 |
Add the binfmt-misc magic needed to register QEMU for handling AArch64
ELF binaries.
Signed-off-by: Peter Maydell <address@hidden>
---
scripts/qemu-binfmt-conf.sh | 3 +++
1 file changed, 3 insertions(+)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index 0da2618..289b1a3 100644
--- a/scripts/qemu-binfmt-conf.sh
+++ b/scripts/qemu-binfmt-conf.sh
@@ -41,6 +41,9 @@ if [ $cpu != "arm" ] ; then
echo
':arm:M::\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28\x00:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff:/usr/local/bin/qemu-arm:'
> /proc/sys/fs/binfmt_misc/register
echo
':armeb:M::\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x28:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff:/usr/local/bin/qemu-armeb:'
> /proc/sys/fs/binfmt_misc/register
fi
+if [ $cpu != "aarch64" ] ; then
+ echo
':aarch64:M::\x7fELF\x02\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\xb7\x00:\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff:/usr/local/bin/qemu-aarch64:'
> /proc/sys/fs/binfmt_misc/register
+fi
if [ $cpu != "sparc" ] ; then
echo
':sparc:M::\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x02:\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff:/usr/local/bin/qemu-sparc:'
> /proc/sys/fs/binfmt_misc/register
fi
--
1.9.0
- [Qemu-devel] [PATCH v2 17/25] target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL, (continued)
- [Qemu-devel] [PATCH v2 17/25] target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 03/25] target-arm: A64: Add last AdvSIMD Integer to FP ops, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 18/25] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 16/25] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 09/25] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement SRI, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 12/25] target-arm: A64: List unsupported shift-imm opcodes, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 04/25] target-arm: A64: Add FSQRT to C3.6.17 (two misc), Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 22/25] target-arm: A64: Implement scalar saturating narrow ops, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 02/25] target-arm: A64: Fix bug in add_sub_ext handling of rn, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 25/25] scripts/qemu-binfmt-conf.sh: Add AArch64 registration,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 01/25] target-arm: A64: Implement PMULL instruction, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 13/25] target-arm: A64: Add FRECPX (reciprocal exponent), Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 20/25] target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE, Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 24/25] target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate), Peter Maydell, 2014/03/14
- [Qemu-devel] [PATCH v2 11/25] target-arm: A64: Implement FCVTL, Peter Maydell, 2014/03/14
- Re: [Qemu-devel] [PATCH v2 00/25] A64: Neon patches, sixth set, Richard Henderson, 2014/03/14