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[Qemu-devel] [PATCH v3 7/7] allwinner-emac: update irq status after writ
From: |
Beniamino Galvani |
Subject: |
[Qemu-devel] [PATCH v3 7/7] allwinner-emac: update irq status after writes to interrupt registers |
Date: |
Sat, 15 Mar 2014 14:01:33 +0100 |
The irq line status must be updated after writes to the INT_CTL and
INT_STA registers.
Signed-off-by: Beniamino Galvani <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
hw/net/allwinner_emac.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c
index 91931ac..d780ba0 100644
--- a/hw/net/allwinner_emac.c
+++ b/hw/net/allwinner_emac.c
@@ -391,9 +391,11 @@ static void aw_emac_write(void *opaque, hwaddr offset,
uint64_t value,
break;
case EMAC_INT_CTL_REG:
s->int_ctl = value;
+ aw_emac_update_irq(s);
break;
case EMAC_INT_STA_REG:
s->int_sta &= ~value;
+ aw_emac_update_irq(s);
break;
case EMAC_MAC_MADR_REG:
s->phy_target = value;
--
1.7.10.4
- [Qemu-devel] [PATCH v3 0/7] Allwinner A10 fixes, Beniamino Galvani, 2014/03/15
- [Qemu-devel] [PATCH v3 1/7] allwinner-a10-pic: set vector address when an interrupt is pending, Beniamino Galvani, 2014/03/15
- [Qemu-devel] [PATCH v3 2/7] allwinner-a10-pic: fix behaviour of pending register, Beniamino Galvani, 2014/03/15
- [Qemu-devel] [PATCH v3 3/7] allwinner-a10-pit: avoid generation of spurious interrupts, Beniamino Galvani, 2014/03/15
- [Qemu-devel] [PATCH v3 7/7] allwinner-emac: update irq status after writes to interrupt registers,
Beniamino Galvani <=
- [Qemu-devel] [PATCH v3 4/7] allwinner-a10-pit: use level triggered interrupts, Beniamino Galvani, 2014/03/15
- [Qemu-devel] [PATCH v3 5/7] allwinner-a10-pit: implement prescaler and source selection, Beniamino Galvani, 2014/03/15
- [Qemu-devel] [PATCH v3 6/7] allwinner-emac: set autonegotiation complete bit on link up, Beniamino Galvani, 2014/03/15