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[Qemu-devel] [PATCH 07/14] tcg-sparc: Implement muls2_i32
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 07/14] tcg-sparc: Implement muls2_i32 |
Date: |
Mon, 17 Mar 2014 11:37:49 -0700 |
Using the 32-bit SMUL is a tad more efficient than
resorting to extending and using the 64-bit MULX.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/sparc/tcg-target.c | 18 +++++++++++++++---
tcg/sparc/tcg-target.h | 2 +-
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index d086c10..43ede5b 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -200,6 +200,7 @@ static const int tcg_target_call_oarg_regs[] = {
#define ARITH_ADDX (INSN_OP(2) | INSN_OP3(0x08))
#define ARITH_SUBX (INSN_OP(2) | INSN_OP3(0x0c))
#define ARITH_UMUL (INSN_OP(2) | INSN_OP3(0x0a))
+#define ARITH_SMUL (INSN_OP(2) | INSN_OP3(0x0b))
#define ARITH_UDIV (INSN_OP(2) | INSN_OP3(0x0e))
#define ARITH_SDIV (INSN_OP(2) | INSN_OP3(0x0f))
#define ARITH_MULX (INSN_OP(2) | INSN_OP3(0x09))
@@ -1284,9 +1285,19 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc, const TCGArg *args,
ARITH_SUBCC, ARITH_SUBX);
break;
case INDEX_op_mulu2_i32:
- tcg_out_arithc(s, args[0], args[2], args[3], const_args[3],
- ARITH_UMUL);
- tcg_out_rdy(s, args[1]);
+ c = ARITH_UMUL;
+ goto do_mul2;
+ case INDEX_op_muls2_i32:
+ c = ARITH_SMUL;
+ do_mul2:
+ /* The 32-bit multiply insns produce a full 64-bit result. If the
+ destination register can hold it, we can avoid the slower RDY. */
+ tcg_out_arithc(s, args[0], args[2], args[3], const_args[3], c);
+ if (SPARC64 || args[0] <= TCG_REG_O7) {
+ tcg_out_arithi(s, args[1], args[0], 32, SHIFT_SRLX);
+ } else {
+ tcg_out_rdy(s, args[1]);
+ }
break;
case INDEX_op_qemu_ld_i32:
@@ -1418,6 +1429,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
{ INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rJ", "rJ" } },
{ INDEX_op_mulu2_i32, { "r", "r", "rZ", "rJ" } },
+ { INDEX_op_muls2_i32, { "r", "r", "rZ", "rJ" } },
{ INDEX_op_mov_i64, { "R", "R" } },
{ INDEX_op_movi_i64, { "R" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 5442d45..091224c 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -108,7 +108,7 @@ typedef enum {
#define TCG_TARGET_HAS_add2_i32 1
#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 1
-#define TCG_TARGET_HAS_muls2_i32 0
+#define TCG_TARGET_HAS_muls2_i32 1
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
--
1.8.5.3
- [Qemu-devel] [PATCH 00/14] tcg/sparc v8plus code generation, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 01/14] tcg: Fix missed pointer size != TCG_TARGET_REG_BITS changes, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 02/14] tcg: Add INDEX_op_trunc_i32, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 03/14] tcg-sparc: Remove most uses of TCG_TARGET_REG_BITS, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 04/14] tcg-sparc: Support trunc_i32, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 05/14] tcg-sparc: Use 64-bit registers with sparcv8plus, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 06/14] tcg-sparc: Use the RETURN instruction, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 07/14] tcg-sparc: Implement muls2_i32,
Richard Henderson <=
- [Qemu-devel] [PATCH 08/14] tcg-sparc: Tidy check_fit_* tests, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 09/14] tcg-sparc: Don't handle mov/movi in tcg_out_op, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 10/14] tcg-sparc: Hoist common argument loads in tcg_out_op, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 11/14] tcg-sparc: Fixup function argument types, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 12/14] tcg-sparc: Fix small 32-bit movi, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 13/14] tcg-sparc: Fix 32-bit constant arguments tests, Richard Henderson, 2014/03/17
- [Qemu-devel] [PATCH 14/14] tcg-sparc: Accept stores of zero, Richard Henderson, 2014/03/17