[Qemu-devel] [PATCH v2 1/7] target-arm: Decouple AArch64 cp registers

[Alvise Rigo]

Relying on the AArch64 views for the migration of cp registers values
makes impossible to have a successful migration between TCG and KVM
because the latter uses the AArch32 indexes format: force the AArch32
processor to not generate the cp registers belonging to the 64bit architecture.

Signed-off-by: Alvise Rigo <address@hidden>
---
 target-arm/helper.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index f65cbac..2791dac 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2313,6 +2313,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const 
ARMCPRegInfo *r,
     /* Private utility function for define_one_arm_cp_reg_with_opaque():
      * add a single reginfo struct to the hash table.
      */
+    CPUARMState *env = &cpu->env;
+    int is_a64 = arm_feature(env, ARM_FEATURE_AARCH64);
+    if (((r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA64
+        && !is_a64) || (r->state == ARM_CP_STATE_AA64 && !is_a64))) {
+        /* no need of the AArch64 cp definition */
+        return;
+    }
+
     uint32_t *key = g_new(uint32_t, 1);
     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
@@ -2322,9 +2330,12 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const 
ARMCPRegInfo *r,
          * view handles that. AArch64 also handles reset.
          * We assume it is a cp15 register.
          */
+        if (is_a64) {
+            /* this is an AArch64 view */
+            r2->type |= ARM_CP_NO_MIGRATE;
+            r2->resetfn = arm_cp_reset_ignore;
+        }
         r2->cp = 15;
-        r2->type |= ARM_CP_NO_MIGRATE;
-        r2->resetfn = arm_cp_reset_ignore;
 #ifdef HOST_WORDS_BIGENDIAN
         if (r2->fieldoffset) {
             r2->fieldoffset += sizeof(uint32_t);
-- 
1.8.3.2