Re: [Qemu-devel] [Qemu-ppc] target-ppc: Problem with mtmsr emulation

[Tom Musta]

On 3/28/2014 9:36 AM, Tom Musta wrote:
> I agree with Alex that a flags based approach could be used to support the L 
> bit for
> Book III-S models and to ignore the L bit for Book III-E models.  The 
> question is
> which flag(s) can we use?  Let me see if I can find out.

I looked at this a bit more.  I do not see any good correlation with the 
existing
instruction flags.

I do see some good correlation with the exception flags. But there are 
problems: One
challenge that I see is that the exception flags are not (currently) available 
in the
context structure passed to the generators (DisasContext). The other problem is 
that
this has the same brittleness that Alex was observing about adding new models 
and
needing to remember all the little bits to be set (different thread yesterday).

Given this, I think a reasonable way to proceed would be to:

  (a) add an explicit instruction flag for L bit support (e.g. PPC2_MTMSR_L)
  (b) remove the bit from the reserved bits mask
  (c) add some additional logic to the mtmsr[d] generators to gate the L=1 path.
  (d) add the new flag to the more recent models that support Book III-S.

And I still think there might be a bug in the L=0 Book III-S path.