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[Qemu-devel] [PATCH v6 27/37] target-arm: Remove THUMB2EE feature from A
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v6 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU |
Date: |
Thu, 10 Apr 2014 17:15:26 +0100 |
The AArch64 usermode 'any' CPU type was accidentally specified
with the ARM_FEATURE_THUMB2EE bit set. This is incorrect since
ARMv8 removes Thumb2EE completely. Since we never implemented
Thumb2EE anyway having the feature bit set was fairly harmless
for user-mode, but the correct thing is to not set it at all.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
---
target-arm/cpu64.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 5be7d72..b8b4fa6 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -83,7 +83,6 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_VFP4);
set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
- set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
set_feature(&cpu->env, ARM_FEATURE_V7MP);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
--
1.9.1
- Re: [Qemu-devel] [PATCH v6 16/37] target-arm: Implement SP_EL0, SP_EL1, (continued)
- [Qemu-devel] [PATCH v6 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 32/37] target-arm: Implement RVBAR register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 34/37] target-arm: Implement CBAR for Cortex-A57, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 19/37] target-arm: Implement AArch64 EL1 exception handling, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 20/37] target-arm: Implement ARMv8 MVFR registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 12/37] target-arm: A64: Implement DC ZVA, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU,
Peter Maydell <=
- [Qemu-devel] [PATCH v6 26/37] target-arm: Implement ISR_EL1 register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 01/37] target-arm: Split out private-to-target functions into internals.h, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 11/37] target-arm: Don't mention PMU in debug feature register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones for ARMv8, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 10/37] target-arm: Add v8 mmu translation support, Peter Maydell, 2014/04/10