Re: [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers

[Peter Crosthwaite]

On Fri, Apr 11, 2014 at 2:15 AM, Peter Maydell <address@hidden> wrote:
> Implement the auxiliary fault status registers AFSR0_EL1 and
> AFSR1_EL1. These are present on v7 and later, and have IMPDEF
> behaviour; we choose to RAZ/WI for all cores.
>
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Peter Crosthwaite <address@hidden>

FWIW, I think .type = ARM_CP_UNIMP might be worthwhile.

> ---
>  target-arm/helper.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 1d1e7b4..988a8e9 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -784,6 +784,15 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
>      { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
>        .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    /* Auxiliary fault status registers: these also are IMPDEF, and we
> +     * choose to RAZ/WI for all cores.
> +     */
> +    { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
> +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
> +      .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
>      /* MAIR can just read-as-written because we don't implement caches
>       * and so don't need to care about memory attributes.
>       */
> --
> 1.9.1
>
>