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Re: [Qemu-devel] [PATCH v6 00/37] AArch64 system emulation
From: |
Peter Crosthwaite |
Subject: |
Re: [Qemu-devel] [PATCH v6 00/37] AArch64 system emulation |
Date: |
Mon, 14 Apr 2014 16:39:18 +1000 |
On Fri, Apr 11, 2014 at 8:43 AM, Peter Crosthwaite
<address@hidden> wrote:
> On Fri, Apr 11, 2014 at 2:14 AM, Peter Maydell <address@hidden> wrote:
>> Here's v5 of the AArch64 system emulation patchset.
>> Still missing/TODO:
>> * SMP support (needs PSCI emulation in QEMU; being prototyped)
>> * save/restore (I have a patch which adds this but I think it will
>> look better if we consolidate AArch32 cpsr and AArch64 pstate
>> handling)
>> but both of these I think are best done once this main series
>> is committed to master.
>>
>> The changes v5->v6 are pretty minor, and these patches have
>> been kicking around onlist for a long time, so I plan to
>> put these in a pull request pretty much as soon as we reopen
>> trunk after 2.0 releases. Last chance for review!
>>
>
> Ill do another sweep before the end of the week and review those Ive
> skipped over so far for completeness.
>
Hi Peter,
Im finished with the review. There's a few areas that I'm not very
familiar with that Ive skipped or others have reviewed. So for all
un-commented patches:
Acked-by: Peter Crosthwaite <address@hidden>
Regards,
Peter
> Regards,
> Peter
>
>>
>> Changes v5->v6:
>> * add extract64() when putting together 32-bit CBAR value
>> * be consistent about int vs bool for 1 bit fields in the
>> syn_insn_abort/syn_data_abort functions
>> * added some FIXMEs about inaccurate syndrome info for A32/T32
>> Neon unallocated insns when FP is disabled
>> * decided that using a15mpcore_priv in the virt machine is actually
>> the best approach, and added a suitable comment
>> Changes v4->v5:
>> * new patches:
>> + MVFR registers
>> + various extra system registers
>> + don't expose wildcards for ARMv8
>> + make A15's CBAR R/O
>> + support interprocessing in set_pc
>> * minor tweaks per review (I haven't always taken the review
>> suggestion; see mail threads on the previous version of the
>> patch series)
>> * DC ZVA: use helper_ret_stb_mmu
>> make tlb_vaddr_to_host take param for access type
>> * NB: I didn't make gen_exception and gen_exception_internal shared
>> in patch 5: I think keeping the A64 and A32 decoders independent
>> is preferable
>> * have syn_insn_abort and syn_data_abort set the syndrome bit
>> for 'exception to same level' rather than making caller do it
>> Changes v3->v4:
>> * reviewed patches from bottom of stack got committed to master
>> * new patches at top of stack
>> * addressed review issues on v8 mmu translation patch and DAIF patch
>>
>> thanks
>> -- PMM
>>
>>
>> Peter Maydell (33):
>> target-arm: Split out private-to-target functions into internals.h
>> target-arm: Implement AArch64 DAIF system register
>> target-arm: Define exception record for AArch64 exceptions
>> target-arm: Provide correct syndrome information for cpreg access
>> traps
>> target-arm: Add support for generating exceptions with syndrome
>> information
>> target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
>> target-arm: A64: Add assertion that FP access was checked
>> target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
>> target-arm: Don't mention PMU in debug feature register
>> target-arm: A64: Implement DC ZVA
>> target-arm: Use dedicated CPU state fields for ARM946 access bit
>> registers
>> target-arm: Add AArch64 ELR_EL1 register.
>> target-arm: Implement SP_EL0, SP_EL1
>> target-arm: Implement AArch64 SPSR_EL1
>> target-arm: Move arm_log_exception() into internals.h
>> target-arm: Implement ARMv8 MVFR registers
>> target-arm: Add Cortex-A57 processor
>> hw/arm/virt: Add support for Cortex-A57
>> target-arm: Implement AArch64 views of AArch32 ID registers
>> target-arm: Implement AArch64 view of CONTEXTIDR
>> target-arm: Implement AArch64 view of ACTLR
>> target-arm: Implement ISR_EL1 register
>> target-arm: Remove THUMB2EE feature from AArch64 'any' CPU
>> target-arm: Don't expose wildcard ID register definitions for ARMv8
>> target-arm: Replace wildcarded cpreg definitions with precise ones for
>> ARMv8
>> target-arm: Implement auxiliary fault status registers
>> target-arm: Implement AArch64 address translation operations
>> target-arm: Implement RVBAR register
>> target-arm: Implement Cortex-A57 implementation-defined system
>> registers
>> target-arm: Implement CBAR for Cortex-A57
>> target-arm: Make Cortex-A15 CBAR read-only
>> target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
>> target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32
>>
>> Rob Herring (4):
>> target-arm: Provide syndrome information for MMU faults
>> target-arm: Add v8 mmu translation support
>> target-arm: Implement AArch64 views of fault status and data registers
>> target-arm: Implement AArch64 EL1 exception handling
>>
>> hw/arm/virt.c | 8 +
>> include/exec/softmmu_exec.h | 52 +++
>> linux-user/main.c | 56 ++-
>> target-arm/cpu-qom.h | 10 +-
>> target-arm/cpu.c | 30 +-
>> target-arm/cpu.h | 81 +++--
>> target-arm/cpu64.c | 115 ++++++-
>> target-arm/helper-a64.c | 75 ++++
>> target-arm/helper.c | 809
>> +++++++++++++++++++++++++++++++++-----------
>> target-arm/helper.h | 7 +-
>> target-arm/internals.h | 267 +++++++++++++++
>> target-arm/kvm32.c | 19 +-
>> target-arm/kvm64.c | 71 +++-
>> target-arm/machine.c | 13 +-
>> target-arm/op_helper.c | 92 ++++-
>> target-arm/translate-a64.c | 441 +++++++++++++++++++++---
>> target-arm/translate.c | 195 ++++++++---
>> target-arm/translate.h | 23 +-
>> 18 files changed, 1987 insertions(+), 377 deletions(-)
>> create mode 100644 target-arm/internals.h
>>
>> --
>> 1.9.1
>>
>>
- Re: [Qemu-devel] [PATCH v6 31/37] target-arm: Implement AArch64 address translation operations, (continued)
- [Qemu-devel] [PATCH v6 25/37] target-arm: Implement AArch64 view of ACTLR, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 15/37] target-arm: Add AArch64 ELR_EL1 register., Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 02/37] target-arm: Implement AArch64 DAIF system register, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 08/37] target-arm: A64: Add assertion that FP access was checked, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 07/37] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set, Peter Maydell, 2014/04/10
- [Qemu-devel] [PATCH v6 28/37] target-arm: Don't expose wildcard ID register definitions for ARMv8, Peter Maydell, 2014/04/10
- Re: [Qemu-devel] [PATCH v6 00/37] AArch64 system emulation, Peter Crosthwaite, 2014/04/10
- Re: [Qemu-devel] [PATCH v6 00/37] AArch64 system emulation,
Peter Crosthwaite <=