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[Qemu-devel] [PATCH 2/3] target-arm: introduce be8 tbflag
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From: |
Paolo Bonzini |
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Subject: |
[Qemu-devel] [PATCH 2/3] target-arm: introduce be8 tbflag |
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Date: |
Mon, 21 Apr 2014 13:43:39 -0400 |
The tb flag for be8 mode comes from the CPSR E bit. This will let us
implement setend in the next patch.
Signed-off-by: Paolo Bonzini <address@hidden>
---
linux-user/main.c | 1 +
target-arm/cpu.h | 7 +++++++
target-arm/translate.c | 29 +++++++++++++++++++----------
target-arm/translate.h | 1 +
4 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index af924dc..d1e29bf 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -4200,6 +4200,7 @@ int main(int argc, char **argv, char **envp)
if (EF_ARM_EABI_VERSION(info->elf_flags) >= EF_ARM_EABI_VER4
&& (info->elf_flags & EF_ARM_BE8)) {
env->bswap_code = 1;
+ env->uncached_cpsr = CPSR_E;
}
}
#elif defined(TARGET_UNICORE32)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index bf37cd6..70b1a4a 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1109,6 +1109,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE_SHIFT 16
#define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_BE8_SHIFT 17
+#define ARM_TBFLAG_BE8_MASK (1 << ARM_TBFLAG_BE8_SHIFT)
/* Bit usage when in AArch64 state */
#define ARM_TBFLAG_AA64_EL_SHIFT 0
@@ -1131,6 +1133,8 @@ static inline int cpu_mmu_index (CPUARMState *env)
(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
#define ARM_TBFLAG_BSWAP_CODE(F) \
(((F) & ARM_TBFLAG_BSWAP_CODE_MASK) >> ARM_TBFLAG_BSWAP_CODE_SHIFT)
+#define ARM_TBFLAG_BE8(F) \
+ (((F) & ARM_TBFLAG_BE8_MASK) >> ARM_TBFLAG_BE8_SHIFT)
#define ARM_TBFLAG_AA64_EL(F) \
(((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT)
@@ -1157,6 +1161,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
if (privmode) {
*flags |= ARM_TBFLAG_PRIV_MASK;
}
+ if (env->uncached_cpsr & CPSR_E) {
+ *flags |= ARM_TBFLAG_BE8_MASK;
+ }
if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) {
*flags |= ARM_TBFLAG_VFPEN_MASK;
}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 6ca2f6a..1b66798 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -828,23 +828,27 @@ static inline void store_reg_from_load(CPUARMState *env,
DisasContext *s,
#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
- tcg_gen_qemu_ld_i32(val, addr, index, OPC); \
+ int opc = (OPC) | (s->be8 ? MO_BE : MO_LE); \
+ tcg_gen_qemu_ld_i32(val, addr, index, opc); \
}
#define DO_GEN_ST(SUFF, OPC) \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
- tcg_gen_qemu_st_i32(val, addr, index, OPC); \
+ int opc = (OPC) | (s->be8 ? MO_BE : MO_LE); \
+ tcg_gen_qemu_st_i32(val, addr, index, opc); \
}
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
- tcg_gen_qemu_ld_i64(val, addr, index, MO_TEQ);
+ int opc = MO_Q | (s->be8 ? MO_BE : MO_LE);
+ tcg_gen_qemu_ld_i64(val, addr, index, opc);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
- tcg_gen_qemu_st_i64(val, addr, index, MO_TEQ);
+ int opc = MO_Q | (s->be8 ? MO_BE : MO_LE);
+ tcg_gen_qemu_st_i64(val, addr, index, opc);
}
#else
@@ -852,34 +856,38 @@ static inline void gen_aa32_st64(DisasContext *s,
TCGv_i64 val, TCGv_i32 addr, i
#define DO_GEN_LD(SUFF, OPC) \
static inline void gen_aa32_ld##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
+ int opc = (OPC) | (s->be8 ? MO_BE : MO_LE); \
TCGv addr64 = tcg_temp_new(); \
tcg_gen_extu_i32_i64(addr64, addr); \
- tcg_gen_qemu_ld_i32(val, addr64, index, OPC); \
+ tcg_gen_qemu_ld_i32(val, addr64, index, opc); \
tcg_temp_free(addr64); \
}
#define DO_GEN_ST(SUFF, OPC) \
static inline void gen_aa32_st##SUFF(DisasContext *s, TCGv_i32 val, TCGv_i32
addr, int index) \
{ \
+ int opc = (OPC) | (s->be8 ? MO_BE : MO_LE); \
TCGv addr64 = tcg_temp_new(); \
tcg_gen_extu_i32_i64(addr64, addr); \
- tcg_gen_qemu_st_i32(val, addr64, index, OPC); \
+ tcg_gen_qemu_st_i32(val, addr64, index, opc); \
tcg_temp_free(addr64); \
}
static inline void gen_aa32_ld64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
+ int opc = MO_Q | (s->be8 ? MO_BE : MO_LE);
TCGv addr64 = tcg_temp_new();
tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_ld_i64(val, addr64, index, MO_TEQ);
+ tcg_gen_qemu_ld_i64(val, addr64, index, opc);
tcg_temp_free(addr64);
}
static inline void gen_aa32_st64(DisasContext *s, TCGv_i64 val, TCGv_i32 addr,
int index)
{
+ int opc = MO_Q | (s->be8 ? MO_BE : MO_LE);
TCGv addr64 = tcg_temp_new();
tcg_gen_extu_i32_i64(addr64, addr);
- tcg_gen_qemu_st_i64(val, addr64, index, MO_TEQ);
+ tcg_gen_qemu_st_i64(val, addr64, index, opc);
tcg_temp_free(addr64);
}
@@ -7331,7 +7339,7 @@ static void disas_arm_insn(CPUARMState * env,
DisasContext *s)
if ((insn & 0x0ffffdff) == 0x01010000) {
ARCH(6);
/* setend */
- if (((insn >> 9) & 1) != s->bswap_code) {
+ if (((insn >> 9) & 1) != s->be8) {
/* Dynamic endianness switching not implemented. */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
goto illegal_op;
@@ -10464,7 +10472,7 @@ static void disas_thumb_insn(CPUARMState *env,
DisasContext *s)
case 2:
/* setend */
ARCH(6);
- if (((insn >> 3) & 1) != s->bswap_code) {
+ if (((insn >> 3) & 1) != s->be8) {
/* Dynamic endianness switching not implemented. */
qemu_log_mask(LOG_UNIMP, "arm: unimplemented setend\n");
goto illegal_op;
@@ -10644,6 +10652,7 @@ static inline void
gen_intermediate_code_internal(ARMCPU *cpu,
dc->aarch64 = 0;
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->bswap_code = ARM_TBFLAG_BSWAP_CODE(tb->flags);
+ dc->be8 = ARM_TBFLAG_BE8(tb->flags);
dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4;
#if !defined(CONFIG_USER_ONLY)
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 2f491f9..c93efad 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -17,6 +17,7 @@ typedef struct DisasContext {
int singlestep_enabled;
int thumb;
int bswap_code;
+ int be8;
#if !defined(CONFIG_USER_ONLY)
int user;
#endif
--
1.8.5.3