[Qemu-devel] [V2 PATCH 20/37] target-ppc: Introduce DFP Divide

[Tom Musta]

Add emulation of the PowerPC Decimal Floating Point Divide instructions
ddiv[q][.]

Signed-off-by: Tom Musta <address@hidden>
---
V2: Make post-processor list static const per Richard Henderson's review.

 target-ppc/dfp_helper.c |   38 ++++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h     |    2 ++
 target-ppc/translate.c  |    4 ++++
 3 files changed, 44 insertions(+), 0 deletions(-)

diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index c7fda21..aa66a97 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -227,6 +227,13 @@ static void dfp_check_for_XX(struct PPC_DFP *dfp)
     }
 }
 
+static void dfp_check_for_ZX(struct PPC_DFP *dfp)
+{
+    if (dfp->context.status & DEC_Division_by_zero) {
+        dfp_set_FPSCR_flag(dfp, FP_ZX, FP_ZE);
+    }
+}
+
 static void dfp_check_for_VXSNAN(struct PPC_DFP *dfp)
 {
     if (dfp->context.status & DEC_Invalid_operation) {
@@ -269,6 +276,22 @@ static void dfp_check_for_VXIMZ(struct PPC_DFP *dfp)
     }
 }
 
+static void dfp_check_for_VXZDZ(struct PPC_DFP *dfp)
+{
+    if (dfp->context.status & DEC_Division_undefined) {
+        dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXZDZ, FP_VE);
+    }
+}
+
+static void dfp_check_for_VXIDI(struct PPC_DFP *dfp)
+{
+    if (dfp->context.status & DEC_Invalid_operation) {
+        if (decNumberIsInfinite(&dfp->a) && decNumberIsInfinite(&dfp->b)) {
+            dfp_set_FPSCR_flag(dfp, FP_VX | FP_VXIDI, FP_VE);
+        }
+    }
+}
+
 #define DFP_HELPER_TAB(op, dnop, postprocs, size)                              
\
 void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *a, uint64_t *b)      
\
 {                                                                              
\
@@ -322,3 +345,18 @@ static void MUL_PPs(struct PPC_DFP *dfp)
 
 DFP_HELPER_TAB(dmul, decNumberMultiply, MUL_PPs, 64)
 DFP_HELPER_TAB(dmulq, decNumberMultiply, MUL_PPs, 128)
+
+static void DIV_PPs(struct PPC_DFP *dfp)
+{
+    dfp_set_FPRF_from_FRT(dfp);
+    dfp_check_for_OX(dfp);
+    dfp_check_for_UX(dfp);
+    dfp_check_for_ZX(dfp);
+    dfp_check_for_XX(dfp);
+    dfp_check_for_VXSNAN(dfp);
+    dfp_check_for_VXZDZ(dfp);
+    dfp_check_for_VXIDI(dfp);
+}
+
+DFP_HELPER_TAB(ddiv, decNumberDivide, DIV_PPs, 64)
+DFP_HELPER_TAB(ddivq, decNumberDivide, DIV_PPs, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 17c75ab..93342ea 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -624,4 +624,6 @@ DEF_HELPER_4(dsub, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(dsubq, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(dmul, void, env, fprp, fprp, fprp)
 DEF_HELPER_4(dmulq, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(ddiv, void, env, fprp, fprp, fprp)
+DEF_HELPER_4(ddivq, void, env, fprp, fprp, fprp)
 #include "exec/def-helper.h"
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a36ead4..1c2c49f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8362,6 +8362,8 @@ GEN_DFP_T_A_B_Rc(dsub)
 GEN_DFP_T_A_B_Rc(dsubq)
 GEN_DFP_T_A_B_Rc(dmul)
 GEN_DFP_T_A_B_Rc(dmulq)
+GEN_DFP_T_A_B_Rc(ddiv)
+GEN_DFP_T_A_B_Rc(ddivq)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11295,6 +11297,8 @@ GEN_DFP_T_A_B_Rc(dsub, 0x02, 0x10),
 GEN_DFP_Tp_Ap_Bp_Rc(dsubq, 0x02, 0x10),
 GEN_DFP_T_A_B_Rc(dmul, 0x02, 0x01),
 GEN_DFP_Tp_Ap_Bp_Rc(dmulq, 0x02, 0x01),
+GEN_DFP_T_A_B_Rc(ddiv, 0x02, 0x11),
+GEN_DFP_Tp_Ap_Bp_Rc(ddivq, 0x02, 0x11),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, 
PPC_NONE)
-- 
1.7.1