[Qemu-devel] [V2 PATCH 28/37] target-ppc: Introduce DFP Round to Integer

[Tom Musta]

Add emulation of the PowerPC Decimal Floating Point (DFP) Round
to FP Integer With Inexact (drintx[q][.]) and DFP Round to FP
Integer Without Inexact (drintn[q][.]) instructions.

Signed-off-by: Tom Musta <address@hidden>
---
V2: Make post-processor list static const per Richard Henderson's review.

 target-ppc/dfp_helper.c |   40 ++++++++++++++++++++++++++++++++++++++++
 target-ppc/helper.h     |    4 ++++
 target-ppc/translate.c  |    8 ++++++++
 3 files changed, 52 insertions(+), 0 deletions(-)

diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index dd67ad2..cc5788d 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -797,3 +797,43 @@ void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t 
*a,            \
 
 DFP_HELPER_RRND(drrnd, 64)
 DFP_HELPER_RRND(drrndq, 128)
+
+#define DFP_HELPER_RINT(op, postprocs, size)                                   
\
+void helper_##op(CPUPPCState *env, uint64_t *t, uint64_t *b,                   
\
+             uint32_t r, uint32_t rmc)                                         
\
+{                                                                              
\
+    struct PPC_DFP dfp;                                                        
\
+                                                                               
\
+    dfp_prepare_decimal##size(&dfp, 0, b, env);                                
\
+                                                                               
\
+    dfp_set_round_mode_from_immediate(r, rmc, &dfp);                           
\
+    decNumberToIntegralExact(&dfp.t, &dfp.b, &dfp.context);                    
\
+    decimal##size##FromNumber((decimal##size *)dfp.t64, &dfp.t, &dfp.context); 
\
+    postprocs(&dfp);                                                           
\
+                                                                               
\
+    if (size == 64) {                                                          
\
+        t[0] = dfp.t64[0];                                                     
\
+    } else if (size == 128) {                                                  
\
+        t[0] = dfp.t64[HI_IDX];                                                
\
+        t[1] = dfp.t64[LO_IDX];                                                
\
+    }                                                                          
\
+}
+
+static void RINTX_PPs(struct PPC_DFP *dfp)
+{
+    dfp_set_FPRF_from_FRT(dfp);
+    dfp_check_for_XX(dfp);
+    dfp_check_for_VXSNAN(dfp);
+}
+
+DFP_HELPER_RINT(drintx, RINTX_PPs, 64)
+DFP_HELPER_RINT(drintxq, RINTX_PPs, 128)
+
+static void RINTN_PPs(struct PPC_DFP *dfp)
+{
+    dfp_set_FPRF_from_FRT(dfp);
+    dfp_check_for_VXSNAN(dfp);
+}
+
+DFP_HELPER_RINT(drintn, RINTN_PPs, 64)
+DFP_HELPER_RINT(drintnq, RINTN_PPs, 128)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index b63affb..2ef18c2 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -644,4 +644,8 @@ DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
 DEF_HELPER_5(dquaq, void, env, fprp, fprp, fprp, i32)
 DEF_HELPER_5(drrnd, void, env, fprp, fprp, fprp, i32)
 DEF_HELPER_5(drrndq, void, env, fprp, fprp, fprp, i32)
+DEF_HELPER_5(drintx, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(drintxq, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(drintn, void, env, fprp, fprp, i32, i32)
+DEF_HELPER_5(drintnq, void, env, fprp, fprp, i32, i32)
 #include "exec/def-helper.h"
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3738012..65b1503 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8382,6 +8382,10 @@ GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
 GEN_DFP_T_A_B_I32_Rc(dquaq, RMC)
 GEN_DFP_T_A_B_I32_Rc(drrnd, RMC)
 GEN_DFP_T_A_B_I32_Rc(drrndq, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintx, FPW, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintxq, FPW, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintn, FPW, RMC)
+GEN_DFP_T_B_U32_U32_Rc(drintnq, FPW, RMC)
 /***                           SPE extension                               ***/
 /* Register moves */
 
@@ -11335,6 +11339,10 @@ GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
 GEN_DFP_Tp_Ap_Bp_RMC_Rc(dquaq, 0x03, 0x00),
 GEN_DFP_T_A_B_RMC_Rc(drrnd, 0x03, 0x01),
 GEN_DFP_Tp_A_Bp_RMC_Rc(drrndq, 0x03, 0x01),
+GEN_DFP_R_T_B_RMC_Rc(drintx, 0x03, 0x03),
+GEN_DFP_R_Tp_Bp_RMC_Rc(drintxq, 0x03, 0x03),
+GEN_DFP_R_T_B_RMC_Rc(drintn, 0x03, 0x07),
+GEN_DFP_R_Tp_Bp_RMC_Rc(drintnq, 0x03, 0x07),
 #undef GEN_SPE
 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
     GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, 
PPC_NONE)
-- 
1.7.1