Re: [Qemu-devel] [patch 1/2] target-i386: support "invariant tsc" flag

[Eduardo Habkost]

On Wed, Apr 23, 2014 at 03:20:03PM -0300, Marcelo Tosatti wrote:
> Expose "Invariant TSC" flag, if KVM is enabled. From Intel documentation:
> 
> 17.13.1 Invariant TSC The time stamp counter in newer processors may
> support an enhancement, referred to as invariant TSC. Processor’s
> support for invariant TSC is indicated by CPUID.80000007H:EDX[8].
> The invariant TSC will run at a constant rate in all ACPI P-, C-.
> and T-states. This is the architectural behavior moving forward. On
> processors with invariant TSC support, the OS may use the TSC for wall
> clock timer services (instead of ACPI or HPET timers). TSC reads are
> much more efficient and do not incur the overhead associated with a ring
> transition or access to a platform resource.
> 
> Signed-off-by: Marcelo Tosatti <address@hidden>

Reviewed-by: Eduardo Habkost <address@hidden>

I plan to rebase this on top of my feature-word-filtering refactor
series ("Support check/enforce flags in TCG mode, too"), and submit it
as part of that series.

-- 
Eduardo