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[Qemu-devel] [PATCH 3/8] target-i386: fix set of registers zeroed on res
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PATCH 3/8] target-i386: fix set of registers zeroed on reset |
Date: |
Tue, 29 Apr 2014 13:54:27 +0200 |
BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
should be (Intel Instruction Set Extensions Programming Reference
319433-015, pages 9-4 and 9-6). Same for YMM.
XCR0 should be reset to 1.
TSC and TSC_RESET were zeroed already by the memset, remove the explicit
assignments.
Cc: Andreas Färber <address@hidden>
Cc: address@hidden
Signed-off-by: Paolo Bonzini <address@hidden>
---
target-i386/cpu.c | 3 +--
target-i386/cpu.h | 11 ++++++-----
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 05c3005..78c1573 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -2477,8 +2477,7 @@ static void x86_cpu_reset(CPUState *s)
cpu_breakpoint_remove_all(s, BP_CPU);
cpu_watchpoint_remove_all(s, BP_CPU);
- env->tsc_adjust = 0;
- env->tsc = 0;
+ env->xcr0 = 1;
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index 2a22a7d..e2244e9 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -797,6 +797,10 @@ typedef struct CPUX86State {
target_ulong cr[5]; /* NOTE: cr1 is unused */
int32_t a20_mask;
+ BNDReg bnd_regs[4];
+ BNDCSReg bndcs_regs;
+ uint64_t msr_bndcfgs;
+
/* FPU state */
unsigned int fpstt; /* top of stack index */
uint16_t fpus;
@@ -819,6 +823,8 @@ typedef struct CPUX86State {
XMMReg xmm_t0;
MMXReg mmx_t0;
+ XMMReg ymmh_regs[CPU_NB_REGS];
+
/* sysenter registers */
uint32_t sysenter_cs;
target_ulong sysenter_esp;
@@ -928,12 +934,7 @@ typedef struct CPUX86State {
uint16_t fpus_vmstate;
uint16_t fptag_vmstate;
uint16_t fpregs_format_vmstate;
-
uint64_t xstate_bv;
- XMMReg ymmh_regs[CPU_NB_REGS];
- BNDReg bnd_regs[4];
- BNDCSReg bndcs_regs;
- uint64_t msr_bndcfgs;
uint64_t xcr0;
--
1.8.3.1
- [Qemu-devel] [PATCH 0/8] x86: correctly implement soft reset, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 3/8] target-i386: fix set of registers zeroed on reset,
Paolo Bonzini <=
- [Qemu-devel] [PATCH 1/8] kvm: reset state from the CPU's reset method, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 5/8] apic: do not accept SIPI on the bootstrap processor, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 4/8] target-i386: preserve FPU and MSR state on INIT, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 2/8] kvm: forward INIT signals coming from the chipset, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 6/8] cpu: make CPU_INTERRUPT_RESET available on all targets, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 7/8] pc: port 92 reset requires a low->high transition, Paolo Bonzini, 2014/04/29
- [Qemu-devel] [PATCH 8/8] x86: correctly implement soft reset, Paolo Bonzini, 2014/04/29