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[Qemu-devel] [PULL 00/10] target-arm queue
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 00/10] target-arm queue |
Date: |
Thu, 1 May 2014 15:54:57 +0100 |
Nothing earthshattering here, but it does have the patch which
actually lets us boot an emulated AArch64 CPU on a board...
thanks
-- PMM
The following changes since commit 051b9980b99dbfba22ea5f79bd3708d513ae121d:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-6' into staging
(2014-05-01 14:17:33 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140501
for you to fetch changes up to f42c5c8ec8aa0e15583487ffee62964830751623:
hw/arm/virt: Add support for Cortex-A57 (2014-05-01 15:25:52 +0100)
----------------------------------------------------------------
target-arm queue:
* implement XScale cache lockdown cp15 ops
* fix v7M CPUID base register
* implement WFE and YIELD as yields for A64
* fix A64 "BLR LR"
* support Cortex-A57 in virt machine model
* a few other minor AArch64 bugfixes
----------------------------------------------------------------
Edgar E. Iglesias (4):
target-arm: Make vbar_write 64bit friendly on 32bit hosts
target-arm: A64: Handle blr lr
target-arm: A64: Fix a typo when declaring TLBI ops
target-arm: Correct a comment refering to EL0
Peter Maydell (4):
target-arm: Implement XScale cache lockdown operations as NOPs
hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv
hw/arm/virt: Put GIC register banks on 64K boundaries
hw/arm/virt: Add support for Cortex-A57
Rabin Vincent (1):
armv7m_nvic: fix CPUID Base Register
Rob Herring (1):
target-arm: implement WFE/YIELD as a yield for AArch64
hw/arm/virt.c | 93 ++++++++++++++++++++++++++++++----------------
hw/intc/armv7m_nvic.c | 2 +-
target-arm/helper.c | 41 +++++++++++++-------
target-arm/op_helper.c | 2 +-
target-arm/translate-a64.c | 9 ++++-
5 files changed, 99 insertions(+), 48 deletions(-)
- [Qemu-devel] [PULL 00/10] target-arm queue,
Peter Maydell <=
- [Qemu-devel] [PULL 08/10] hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 07/10] target-arm: Correct a comment refering to EL0, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 02/10] armv7m_nvic: fix CPUID Base Register, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 05/10] target-arm: A64: Handle blr lr, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 09/10] hw/arm/virt: Put GIC register banks on 64K boundaries, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 01/10] target-arm: Implement XScale cache lockdown operations as NOPs, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 06/10] target-arm: A64: Fix a typo when declaring TLBI ops, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 03/10] target-arm: implement WFE/YIELD as a yield for AArch64, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 04/10] target-arm: Make vbar_write 64bit friendly on 32bit hosts, Peter Maydell, 2014/05/01
- [Qemu-devel] [PULL 10/10] hw/arm/virt: Add support for Cortex-A57, Peter Maydell, 2014/05/01