Re: [Qemu-devel] [PATCH v1 4/5] xilinx_timer: Fix writes into TCSR register

[Peter Crosthwaite]

On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias
<address@hidden> wrote:
> From: Guenter Roeck <address@hidden>
>
> The TCSR register has only 11 valid bits. This is now used by the
> linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
> and later to hang when run under qemu-microblaze. Mask valid bits
> before writing the register to solve the problem.
>
> Signed-off-by: Guenter Roeck <address@hidden>
> Reviewed-by: Edgar E. Iglesias <address@hidden>
> Signed-off-by: Edgar E. Iglesias <address@hidden>
> ---
>  hw/timer/xilinx_timer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
> index 6113b97..3ff1da9 100644
> --- a/hw/timer/xilinx_timer.c
> +++ b/hw/timer/xilinx_timer.c
> @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
>              if (value & TCSR_TINT)
>                  value &= ~TCSR_TINT;
>
> -            xt->regs[addr] = value;
> +            xt->regs[addr] = value & 0x7ff;

In at least the later TRMs, Bit 11 is validly defined as the cascade
bit, taking the total number of bits to 12. I think this mask should
be 0xfff.

Regards,
Peter

>              if (value & TCSR_ENT)
>                  timer_enable(xt);
>              break;
> --
> 1.8.3.2
>
>