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[Qemu-devel] [PATCH v2 2/4] arm_gic: Use new qom_private macro to mark p
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From: |
Peter Maydell |
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Subject: |
[Qemu-devel] [PATCH v2 2/4] arm_gic: Use new qom_private macro to mark private fields |
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Date: |
Fri, 9 May 2014 16:56:02 +0100 |
Use the new qom_private macro infrastructure to mark private fields for
the arm_gic classes.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gic.c | 3 ++
hw/intc/arm_gic_common.c | 2 ++
hw/intc/arm_gic_kvm.c | 2 ++
hw/intc/armv7m_nvic.c | 2 ++
include/hw/intc/arm_gic.h | 12 ++++++--
include/hw/intc/arm_gic_common.h | 62 +++++++++++++++++++++++-----------------
6 files changed, 54 insertions(+), 29 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1532ef9..afe2179 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -18,6 +18,9 @@
* armv7m_nvic device.
*/
+#define IMPLEMENTING_ARM_GIC
+#define IMPLEMENTING_ARM_GIC_COMMON
+
#include "hw/sysbus.h"
#include "gic_internal.h"
#include "qom/cpu.h"
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index 6d884ec..8a2c434 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -18,6 +18,8 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#define IMPLEMENTING_ARM_GIC_COMMON
+
#include "gic_internal.h"
static void gic_pre_save(void *opaque)
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 5038885..792073e 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -19,6 +19,8 @@
* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
+#define IMPLEMENTING_ARM_GIC_COMMON
+
#include "hw/sysbus.h"
#include "sysemu/kvm.h"
#include "kvm_arm.h"
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 9aa8ab2..d68b286 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -10,6 +10,8 @@
* NVIC. Much of that is also implemented here.
*/
+#define IMPLEMENTING_ARM_GIC_COMMON
+
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/arm/arm.h"
diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h
index 0971e37..8d69e02 100644
--- a/include/hw/intc/arm_gic.h
+++ b/include/hw/intc/arm_gic.h
@@ -31,12 +31,20 @@
#define ARM_GIC_GET_CLASS(obj) \
OBJECT_GET_CLASS(ARMGICClass, (obj), TYPE_ARM_GIC)
+#ifdef IMPLEMENTING_ARM_GIC
+#define qom_private
+#else
+#define qom_private QEMU_PRIVATE_ATTR
+#endif
+
typedef struct ARMGICClass {
/*< private >*/
- ARMGICCommonClass parent_class;
+ qom_private ARMGICCommonClass parent_class;
/*< public >*/
- DeviceRealize parent_realize;
+ qom_private DeviceRealize parent_realize;
} ARMGICClass;
+#undef qom_private
+
#endif
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index f6887ed..39211bd 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -44,39 +44,45 @@ typedef struct gic_irq_state {
bool edge_trigger; /* true: edge-triggered, false: level-triggered */
} gic_irq_state;
+#ifdef IMPLEMENTING_ARM_GIC_COMMON
+#define qom_private
+#else
+#define qom_private QEMU_PRIVATE_ATTR
+#endif
+
typedef struct GICState {
/*< private >*/
- SysBusDevice parent_obj;
+ qom_private SysBusDevice parent_obj;
/*< public >*/
- qemu_irq parent_irq[GIC_NCPU];
- bool enabled;
- bool cpu_enabled[GIC_NCPU];
+ qom_private qemu_irq parent_irq[GIC_NCPU];
+ qom_private bool enabled;
+ qom_private bool cpu_enabled[GIC_NCPU];
- gic_irq_state irq_state[GIC_MAXIRQ];
- uint8_t irq_target[GIC_MAXIRQ];
- uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
- uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
- uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
+ qom_private gic_irq_state irq_state[GIC_MAXIRQ];
+ qom_private uint8_t irq_target[GIC_MAXIRQ];
+ qom_private uint8_t priority1[GIC_INTERNAL][GIC_NCPU];
+ qom_private uint8_t priority2[GIC_MAXIRQ - GIC_INTERNAL];
+ qom_private uint16_t last_active[GIC_MAXIRQ][GIC_NCPU];
/* For each SGI on the target CPU, we store 8 bits
* indicating which source CPUs have made this SGI
* pending on the target CPU. These correspond to
* the bytes in the GIC_SPENDSGIR* registers as
* read by the target CPU.
*/
- uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
+ qom_private uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
- uint16_t priority_mask[GIC_NCPU];
- uint16_t running_irq[GIC_NCPU];
- uint16_t running_priority[GIC_NCPU];
- uint16_t current_pending[GIC_NCPU];
+ qom_private uint16_t priority_mask[GIC_NCPU];
+ qom_private uint16_t running_irq[GIC_NCPU];
+ qom_private uint16_t running_priority[GIC_NCPU];
+ qom_private uint16_t current_pending[GIC_NCPU];
/* We present the GICv2 without security extensions to a guest and
* therefore the guest can configure the GICC_CTLR to configure group 1
* binary point in the abpr.
*/
- uint8_t bpr[GIC_NCPU];
- uint8_t abpr[GIC_NCPU];
+ qom_private uint8_t bpr[GIC_NCPU];
+ qom_private uint8_t abpr[GIC_NCPU];
/* The APR is implementation defined, so we choose a layout identical to
* the KVM ABI layout for QEMU's implementation of the gic:
@@ -92,19 +98,19 @@ typedef struct GICState {
* do power management involving powering down and restarting
* the GIC.
*/
- uint32_t apr[GIC_NR_APRS][GIC_NCPU];
+ qom_private uint32_t apr[GIC_NR_APRS][GIC_NCPU];
- uint32_t num_cpu;
+ qom_private uint32_t num_cpu;
- MemoryRegion iomem; /* Distributor */
+ qom_private MemoryRegion iomem; /* Distributor */
/* This is just so we can have an opaque pointer which identifies
* both this GIC and which CPU interface we should be accessing.
*/
- struct GICState *backref[GIC_NCPU];
- MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
- uint32_t num_irq;
- uint32_t revision;
- int dev_fd; /* kvm device fd if backed by kvm vgic support */
+ qom_private struct GICState *backref[GIC_NCPU];
+ qom_private MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
+ qom_private uint32_t num_irq;
+ qom_private uint32_t revision;
+ qom_private int dev_fd; /* kvm device fd if backed by kvm vgic support */
} GICState;
#define TYPE_ARM_GIC_COMMON "arm_gic_common"
@@ -117,11 +123,13 @@ typedef struct GICState {
typedef struct ARMGICCommonClass {
/*< private >*/
- SysBusDeviceClass parent_class;
+ qom_private SysBusDeviceClass parent_class;
/*< public >*/
- void (*pre_save)(GICState *s);
- void (*post_load)(GICState *s);
+ qom_private void (*pre_save)(GICState *s);
+ qom_private void (*post_load)(GICState *s);
} ARMGICCommonClass;
+#undef qom_private
+
#endif
--
1.9.2