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[Qemu-devel] [PATCH v2 2/3] PPC: Allow little-endian user mode.
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From: |
Doug Kwan |
|
Subject: |
[Qemu-devel] [PATCH v2 2/3] PPC: Allow little-endian user mode. |
|
Date: |
Sat, 10 May 2014 02:16:39 -0700 |
This allow running PPC64 little-endian in user mode if target is configured
that way. In PPC64 LE user mode we set MSR.LE during initialization.
Overhaul handling of byteswapping in code generation and mem helpers.
Signed-off-by: Doug Kwan <address@hidden>
---
target-ppc/mem_helper.c | 25 ++++++--
target-ppc/translate.c | 150 +++++++++++++++++---------------------------
target-ppc/translate_init.c | 9 +++
3 files changed, 89 insertions(+), 95 deletions(-)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index f35ed03..0112821 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -28,6 +28,14 @@
//#define DEBUG_OP
+static inline bool needs_byteswap(const CPUPPCState *env) {
+#if defined(TARGET_WORDS_BIGENDIAN)
+ return msr_le;
+#else
+ return !msr_le;
+#endif
+}
+
/*****************************************************************************/
/* Memory load and stores */
@@ -47,7 +55,7 @@ static inline target_ulong addr_add(CPUPPCState *env,
target_ulong addr,
void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
{
for (; reg < 32; reg++) {
- if (msr_le) {
+ if (needs_byteswap(env)) {
env->gpr[reg] = bswap32(cpu_ldl_data(env, addr));
} else {
env->gpr[reg] = cpu_ldl_data(env, addr);
@@ -59,7 +67,7 @@ void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t
reg)
void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
{
for (; reg < 32; reg++) {
- if (msr_le) {
+ if (needs_byteswap(env)) {
cpu_stl_data(env, addr, bswap32((uint32_t)env->gpr[reg]));
} else {
cpu_stl_data(env, addr, (uint32_t)env->gpr[reg]);
@@ -202,6 +210,11 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong
addr, uint32_t reg,
#define LO_IDX 0
#endif
+/* We use msr_le to determine index ordering in a vector. However,
+ byteswapping is not simply controlled by msr_le. We also need to take
+ into account endianness of the target. This is done for the little-endian
+ PPC64 user-mode target. */
+
#define LVE(name, access, swap, element) \
void helper_##name(CPUPPCState *env, ppc_avr_t *r, \
target_ulong addr) \
@@ -210,9 +223,11 @@ target_ulong helper_lscbx(CPUPPCState *env, target_ulong
addr, uint32_t reg,
int adjust = HI_IDX*(n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
- \
if (msr_le) { \
index = n_elems - index - 1; \
+ } \
+ \
+ if (needs_byteswap(env)) { \
r->element[LO_IDX ? index : (adjust - index)] = \
swap(access(env, addr)); \
} else { \
@@ -235,9 +250,11 @@ LVE(lvewx, cpu_ldl_data, bswap32, u32)
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
- \
if (msr_le) { \
index = n_elems - index - 1; \
+ } \
+ \
+ if (needs_byteswap(env)) { \
access(env, addr, swap(r->element[LO_IDX ? index : \
(adjust - index)])); \
} else { \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index e3fcb03..d28ecc2 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -196,6 +196,7 @@ typedef struct DisasContext {
int access_type;
/* Translation flags */
int le_mode;
+ TCGMemOp default_tcg_memop_mask;
#if defined(TARGET_PPC64)
int sf_mode;
int has_cfar;
@@ -210,6 +211,15 @@ typedef struct DisasContext {
uint64_t insns_flags2;
} DisasContext;
+/* Return true iff byteswap is needed in a scalar memop */
+static inline bool need_byteswap(const DisasContext *ctx) {
+#if defined(TARGET_WORDS_BIGENDIAN)
+ return ctx->le_mode;
+#else
+ return !ctx->le_mode;
+#endif
+}
+
/* True when active word size < size of target_long. */
#ifdef TARGET_PPC64
# define NARROW_MODE(C) (!(C)->sf_mode)
@@ -2652,29 +2662,20 @@ static inline void gen_qemu_ld8s(DisasContext *ctx,
TCGv arg1, TCGv arg2)
static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
- if (unlikely(ctx->le_mode)) {
- tcg_gen_bswap16_tl(arg1, arg1);
- }
+ TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
}
static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (unlikely(ctx->le_mode)) {
- tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
- tcg_gen_bswap16_tl(arg1, arg1);
- tcg_gen_ext16s_tl(arg1, arg1);
- } else {
- tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
- }
+ TCGMemOp op = MO_SW | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
}
static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
- if (unlikely(ctx->le_mode)) {
- tcg_gen_bswap32_tl(arg1, arg1);
- }
+ TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
}
static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
@@ -2687,12 +2688,8 @@ static void gen_qemu_ld32u_i64(DisasContext *ctx,
TCGv_i64 val, TCGv addr)
static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (unlikely(ctx->le_mode)) {
- tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
- tcg_gen_bswap32_tl(arg1, arg1);
- tcg_gen_ext32s_tl(arg1, arg1);
- } else
- tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
+ TCGMemOp op = MO_SL | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
}
static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
@@ -2705,10 +2702,8 @@ static void gen_qemu_ld32s_i64(DisasContext *ctx,
TCGv_i64 val, TCGv addr)
static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
- tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
- if (unlikely(ctx->le_mode)) {
- tcg_gen_bswap64_i64(arg1, arg1);
- }
+ TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
}
static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
@@ -2718,28 +2713,14 @@ static inline void gen_qemu_st8(DisasContext *ctx, TCGv
arg1, TCGv arg2)
static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (unlikely(ctx->le_mode)) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext16u_tl(t0, arg1);
- tcg_gen_bswap16_tl(t0, t0);
- tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
- tcg_temp_free(t0);
- } else {
- tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
- }
+ TCGMemOp op = MO_UW | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
}
static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (unlikely(ctx->le_mode)) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, arg1);
- tcg_gen_bswap32_tl(t0, t0);
- tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
- tcg_temp_free(t0);
- } else {
- tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
- }
+ TCGMemOp op = MO_UL | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
}
static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
@@ -2752,13 +2733,8 @@ static void gen_qemu_st32_i64(DisasContext *ctx,
TCGv_i64 val, TCGv addr)
static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
- if (unlikely(ctx->le_mode)) {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_bswap64_i64(t0, arg1);
- tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
- tcg_temp_free_i64(t0);
- } else
- tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
+ TCGMemOp op = MO_Q | ctx->default_tcg_memop_mask;
+ tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
}
#define GEN_LD(name, ldop, opc, type) \
@@ -2902,6 +2878,8 @@ static void gen_lq(DisasContext *ctx)
EA = tcg_temp_new();
gen_addr_imm_index(ctx, EA, 0x0F);
+ /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
+ 64-bit byteswap already. */
if (unlikely(ctx->le_mode)) {
gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
gen_addr_add(ctx, EA, EA, 8);
@@ -3020,6 +2998,8 @@ static void gen_std(DisasContext *ctx)
EA = tcg_temp_new();
gen_addr_imm_index(ctx, EA, 0x03);
+ /* We only need to swap high and low halves. gen_qemu_st64 does
+ necessary 64-bit byteswap already. */
if (unlikely(ctx->le_mode)) {
gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
gen_addr_add(ctx, EA, EA, 8);
@@ -3049,23 +3029,20 @@ static void gen_std(DisasContext *ctx)
}
#endif
/*** Integer load and store with byte reverse ***/
+
/* lhbrx */
static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
- if (likely(!ctx->le_mode)) {
- tcg_gen_bswap16_tl(arg1, arg1);
- }
+ TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
+ tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
}
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
/* lwbrx */
static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
- if (likely(!ctx->le_mode)) {
- tcg_gen_bswap32_tl(arg1, arg1);
- }
+ TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
+ tcg_gen_qemu_ld_tl(arg1, arg2, ctx->mem_idx, op);
}
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
@@ -3073,10 +3050,8 @@ GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
/* ldbrx */
static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
- if (likely(!ctx->le_mode)) {
- tcg_gen_bswap64_tl(arg1, arg1);
- }
+ TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
+ tcg_gen_qemu_ld_i64(arg1, arg2, ctx->mem_idx, op);
}
GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
#endif /* TARGET_PPC64 */
@@ -3084,30 +3059,16 @@ GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE,
PPC2_DBRX);
/* sthbrx */
static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (likely(!ctx->le_mode)) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext16u_tl(t0, arg1);
- tcg_gen_bswap16_tl(t0, t0);
- tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
- tcg_temp_free(t0);
- } else {
- tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
- }
+ TCGMemOp op = MO_UW | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
+ tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
}
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
/* stwbrx */
static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (likely(!ctx->le_mode)) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_ext32u_tl(t0, arg1);
- tcg_gen_bswap32_tl(t0, t0);
- tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
- tcg_temp_free(t0);
- } else {
- tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
- }
+ TCGMemOp op = MO_UL | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
+ tcg_gen_qemu_st_tl(arg1, arg2, ctx->mem_idx, op);
}
GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
@@ -3115,14 +3076,8 @@ GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
/* stdbrx */
static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
- if (likely(!ctx->le_mode)) {
- TCGv t0 = tcg_temp_new();
- tcg_gen_bswap64_tl(t0, arg1);
- tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
- tcg_temp_free(t0);
- } else {
- tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
- }
+ TCGMemOp op = MO_Q | (ctx->default_tcg_memop_mask ^ MO_BSWAP);
+ tcg_gen_qemu_st_i64(arg1, arg2, ctx->mem_idx, op);
}
GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
#endif /* TARGET_PPC64 */
@@ -3542,7 +3497,9 @@ static void gen_lfdp(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_FLOAT);
EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0); \
+ gen_addr_imm_index(ctx, EA, 0);
+ /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
+ 64-bit byteswap already. */
if (unlikely(ctx->le_mode)) {
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
tcg_gen_addi_tl(EA, EA, 8);
@@ -3566,6 +3523,8 @@ static void gen_lfdpx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_FLOAT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
+ /* We only need to swap high and low halves. gen_qemu_ld64 does necessary
+ 64-bit byteswap already. */
if (unlikely(ctx->le_mode)) {
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
tcg_gen_addi_tl(EA, EA, 8);
@@ -3714,7 +3673,9 @@ static void gen_stfdp(DisasContext *ctx)
}
gen_set_access_type(ctx, ACCESS_FLOAT);
EA = tcg_temp_new();
- gen_addr_imm_index(ctx, EA, 0); \
+ gen_addr_imm_index(ctx, EA, 0);
+ /* We only need to swap high and low halves. gen_qemu_st64 does necessary
+ 64-bit byteswap already. */
if (unlikely(ctx->le_mode)) {
gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
tcg_gen_addi_tl(EA, EA, 8);
@@ -3738,6 +3699,8 @@ static void gen_stfdpx(DisasContext *ctx)
gen_set_access_type(ctx, ACCESS_FLOAT);
EA = tcg_temp_new();
gen_addr_reg_index(ctx, EA);
+ /* We only need to swap high and low halves. gen_qemu_st64 does necessary
+ 64-bit byteswap already. */
if (unlikely(ctx->le_mode)) {
gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
tcg_gen_addi_tl(EA, EA, 8);
@@ -6691,6 +6654,8 @@ static void glue(gen_, name)(DisasContext *ctx)
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
tcg_gen_andi_tl(EA, EA, ~0xf); \
+ /* We only need to swap high and low halves. gen_qemu_ld64 does necessary \
+ 64-bit byteswap already. */ \
if (ctx->le_mode) { \
gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
tcg_gen_addi_tl(EA, EA, 8); \
@@ -6715,6 +6680,8 @@ static void gen_st##name(DisasContext *ctx)
\
EA = tcg_temp_new(); \
gen_addr_reg_index(ctx, EA); \
tcg_gen_andi_tl(EA, EA, ~0xf); \
+ /* We only need to swap high and low halves. gen_qemu_st64 does necessary \
+ 64-bit byteswap already. */ \
if (ctx->le_mode) { \
gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
tcg_gen_addi_tl(EA, EA, 8); \
@@ -11337,6 +11304,7 @@ static inline void
gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.insns_flags2 = env->insns_flags2;
ctx.access_type = -1;
ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
+ ctx.default_tcg_memop_mask = ctx.le_mode ? MO_LE : MO_BE;
#if defined(TARGET_PPC64)
ctx.sf_mode = msr_is_64bit(env, env->msr);
ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
@@ -11401,7 +11369,7 @@ static inline void
gen_intermediate_code_internal(PowerPCCPU *cpu,
ctx.nip, ctx.mem_idx, (int)msr_ir);
if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
gen_io_start();
- if (unlikely(ctx.le_mode)) {
+ if (unlikely(need_byteswap(&ctx))) {
ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
} else {
ctx.opcode = cpu_ldl_code(env, ctx.nip);
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 4d94015..84381ae 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8418,6 +8418,9 @@ static void ppc_cpu_reset(CPUState *s)
msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
msr |= (target_ulong)1 << MSR_PR;
+#if !defined(TARGET_WORDS_BIGENDIAN)
+ msr |= (target_ulong)1 << MSR_LE; /* Little-endian user mode */
+#endif
#endif
#if defined(TARGET_PPC64)
@@ -8461,6 +8464,12 @@ static void ppc_cpu_reset(CPUState *s)
/* Flush all TLBs */
tlb_flush(s, 1);
+
+#if defined(CONFIG_USER_ONLY) && !defined(TARGET_WORDS_BIGENDIAN)
+ if (!msr_le) {
+ cpu_abort(CPU(cpu), "Cannot set QEMU to little-endian user mode\n");
+ }
+#endif
}
static void ppc_cpu_initfn(Object *obj)
--
1.9.1.423.g4596e3a