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[Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode
From: |
Fabian Aggeler |
Subject: |
[Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode |
Date: |
Tue, 13 May 2014 18:15:50 +0200 |
From: Svetlana Fedoseeva <address@hidden>
Define CPU monitor mode. Adjust core registers banking. Adjust CPU VM
state info. Provide CPU mode name for monitor mode.
Signed-off-by: Svetlana Fedoseeva <address@hidden>
Signed-off-by: Sergey Fedorov <address@hidden>
Signed-off-by: Fabian Aggeler <address@hidden>
---
target-arm/cpu.h | 7 ++++---
target-arm/helper.c | 2 ++
target-arm/machine.c | 6 +++---
target-arm/translate.c | 2 +-
4 files changed, 10 insertions(+), 7 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5eba825..a56d3d6 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -143,9 +143,9 @@ typedef struct CPUARMState {
uint32_t spsr;
/* Banked registers. */
- uint64_t banked_spsr[6];
- uint32_t banked_r13[6];
- uint32_t banked_r14[6];
+ uint64_t banked_spsr[7];
+ uint32_t banked_r13[7];
+ uint32_t banked_r14[7];
/* These hold r8-r12. */
uint32_t usr_regs[5];
@@ -563,6 +563,7 @@ enum arm_cpu_mode {
ARM_CPU_MODE_FIQ = 0x11,
ARM_CPU_MODE_IRQ = 0x12,
ARM_CPU_MODE_SVC = 0x13,
+ ARM_CPU_MODE_MON = 0x16,
ARM_CPU_MODE_ABT = 0x17,
ARM_CPU_MODE_UND = 0x1b,
ARM_CPU_MODE_SYS = 0x1f
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 2b57ad9..c1388eb 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3095,6 +3095,8 @@ int bank_number(int mode)
return 4;
case ARM_CPU_MODE_FIQ:
return 5;
+ case ARM_CPU_MODE_MON:
+ return 6;
}
hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
}
diff --git a/target-arm/machine.c b/target-arm/machine.c
index 810ba27..6c4f7b7 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -238,9 +238,9 @@ const VMStateDescription vmstate_arm_cpu = {
.offset = 0,
},
VMSTATE_UINT32(env.spsr, ARMCPU),
- VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6),
- VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
- VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
+ VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 7),
+ VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 7),
+ VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 7),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64(env.elr_el1, ARMCPU),
diff --git a/target-arm/translate.c b/target-arm/translate.c
index a4d920b..46553fa 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -11047,7 +11047,7 @@ void gen_intermediate_code_pc(CPUARMState *env,
TranslationBlock *tb)
}
static const char *cpu_mode_names[16] = {
- "usr", "fiq", "irq", "svc", "???", "???", "???", "abt",
+ "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
"???", "???", "???", "und", "???", "???", "???", "sys"
};
--
1.8.3.2
- Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, (continued)
Re: [Qemu-devel] [PATCH v2 10/23] target-arm: implement CPACR register logic, Peter Crosthwaite, 2014/05/14
[Qemu-devel] [PATCH v2 03/23] target-arm: adjust TTBCR for Security Extension feature, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 12/23] target-arm: add SDER definition, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 07/23] target-arm: reject switching to monitor mode from non-secure state, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 08/23] target-arm: adjust arm_current_pl() for Security Extensions, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 05/23] target-arm: add CPU Monitor mode,
Fabian Aggeler <=
[Qemu-devel] [PATCH v2 04/23] target-arm: preserve RAO/WI bits of ARMv7 SCTLR, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 22/23] target-arm: implement IRQ/FIQ routing to Monitor mode, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 11/23] target-arm: add NSACR support, Fabian Aggeler, 2014/05/13
[Qemu-devel] [PATCH v2 14/23] target-arm: add banked coprocessor register type and macros, Fabian Aggeler, 2014/05/13