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[Qemu-devel] [PATCH 09/24] tcg-mips: Rearrange register allocation
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 09/24] tcg-mips: Rearrange register allocation |
Date: |
Wed, 14 May 2014 00:17:26 -0700 |
Use FP (also known as S8) as a normal call-saved register.
Include T0 in the allocation order and call-clobbered list
even though it's currently used as a TCG temporary.
Put the argument registers at the end of the allocation order.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/mips/tcg-target.c | 22 +++++++++++++++-------
tcg/mips/tcg-target.h | 8 ++++----
2 files changed, 19 insertions(+), 11 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 4c31027..16b8f7f 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -67,13 +67,14 @@ static const char * const
tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
"k1",
"gp",
"sp",
- "fp",
+ "s8",
"ra",
};
#endif
/* check if we really need so many registers :P */
static const TCGReg tcg_target_reg_alloc_order[] = {
+ /* Call saved registers. */
TCG_REG_S0,
TCG_REG_S1,
TCG_REG_S2,
@@ -82,6 +83,10 @@ static const TCGReg tcg_target_reg_alloc_order[] = {
TCG_REG_S5,
TCG_REG_S6,
TCG_REG_S7,
+ TCG_REG_S8,
+
+ /* Call clobbered registers. */
+ TCG_REG_T0,
TCG_REG_T1,
TCG_REG_T2,
TCG_REG_T3,
@@ -91,12 +96,14 @@ static const TCGReg tcg_target_reg_alloc_order[] = {
TCG_REG_T7,
TCG_REG_T8,
TCG_REG_T9,
- TCG_REG_A0,
- TCG_REG_A1,
- TCG_REG_A2,
- TCG_REG_A3,
+ TCG_REG_V1,
TCG_REG_V0,
- TCG_REG_V1
+
+ /* Argument registers, opposite order of allocation. */
+ TCG_REG_A3,
+ TCG_REG_A2,
+ TCG_REG_A1,
+ TCG_REG_A0,
};
static const TCGReg tcg_target_call_iarg_regs[4] = {
@@ -1646,7 +1653,7 @@ static int tcg_target_callee_save_regs[] = {
TCG_REG_S5,
TCG_REG_S6,
TCG_REG_S7,
- TCG_REG_FP,
+ TCG_REG_S8,
TCG_REG_RA, /* should be last for ABI compliance */
};
@@ -1778,6 +1785,7 @@ static void tcg_target_init(TCGContext *s)
(1 << TCG_REG_A1) |
(1 << TCG_REG_A2) |
(1 << TCG_REG_A3) |
+ (1 << TCG_REG_T0) |
(1 << TCG_REG_T1) |
(1 << TCG_REG_T2) |
(1 << TCG_REG_T3) |
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index 7509fa1..c959d1c 100644
--- a/tcg/mips/tcg-target.h
+++ b/tcg/mips/tcg-target.h
@@ -60,8 +60,11 @@ typedef enum {
TCG_REG_K1,
TCG_REG_GP,
TCG_REG_SP,
- TCG_REG_FP,
+ TCG_REG_S8,
TCG_REG_RA,
+
+ TCG_REG_CALL_STACK = TCG_REG_SP,
+ TCG_AREG0 = TCG_REG_S0,
} TCGReg;
#define TCG_CT_CONST_ZERO 0x100
@@ -69,7 +72,6 @@ typedef enum {
#define TCG_CT_CONST_S16 0x400
/* used for function call generation */
-#define TCG_REG_CALL_STACK TCG_REG_SP
#define TCG_TARGET_STACK_ALIGN 8
#define TCG_TARGET_CALL_STACK_OFFSET 16
#define TCG_TARGET_CALL_ALIGN_ARGS 1
@@ -127,8 +129,6 @@ extern bool use_mips32r2_instructions;
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
#define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
-#define TCG_AREG0 TCG_REG_S0
-
#ifdef __OpenBSD__
#include <machine/sysarch.h>
#else
--
1.9.0
- [Qemu-devel] [PATCH 00/24] tcg mips updates, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 02/24] tcg-mips: Constrain the code_gen_buffer to be within one 256mb segment, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 01/24] tcg-mips: Layout executable and code_gen_buffer, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 03/24] tcg-mips: Use J and JAL opcodes, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 06/24] tcg-mips: Move softmmu slow path out of line, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 04/24] tcg-mips: Fill the exit_tb delay slot, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 07/24] tcg-mips: Convert to new qemu_l/st helpers, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 05/24] tcg-mips: Split large ldst offsets, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 09/24] tcg-mips: Rearrange register allocation,
Richard Henderson <=
- [Qemu-devel] [PATCH 10/24] tcg-mips: Introduce TCG_TMP0, TCG_TMP1, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 11/24] tcg-mips: Use T9 for TCG_TMP1, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 08/24] tcg-mips: Convert to new_ldst, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 13/24] tcg-mips: Name the opcode enumeration, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 12/24] tcg-mips: Use EXT for AND on mips32r2, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 14/24] tcg-mips: Fix subtract immediate range, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 15/24] tcg-mips: Hoist args loads, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 16/24] tcg-mips: Improve add2/sub2, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 17/24] tcg-mips: Commonize opcode implementations, Richard Henderson, 2014/05/14
- [Qemu-devel] [PATCH 18/24] tcg-mips: Simplify setcond, Richard Henderson, 2014/05/14