Re: [Qemu-devel] [PATCH v2 00/23] target-arm: add Security Extensions for CPUs

[Sergey Fedorov]

Can address@hidden be removed from CC list since this mailbox has
been deleted? That was my address when I worked for Samsung. Now sending
to this address results with annoying delivery failure notification.

Thanks,
Sergey.

13.05.2014 20:15, Fabian Aggeler wrote:
> Hi,
>
> This is a rework of the Samsung patches sent last year to add Security 
> Extensions. The patches have been changed based on the discussion on
> the mailing list. Other changes became necessary because of Aarch64
> support which got added in the meantime. This patchset makes it possible
> to run a kernel in the secure world and then switch to non-secure
> on CPUs that implement Security Extensions. It works for EL3 in Aarch32
> state, but may add _EL3 registers where necessary to reflect the mapping
> of secure instances of cp registers to _EL3 registers.
>
> Banking of cp registers has been changed from active mass-swapping to
> the mechanism discussed on the mailing list, where every Aarch32 cp 
> register goes into the hashtable twice. A ns-bit is added to the key
> of the register which is used when accessing a cp register to get the
> correct instance.
>
> Magic numbers have been changed to bitshifted constants or macros to make
> the code easier to read.
>
> The whole patchset now uses the term Security Extensions instead of 
> TrustZone as this is the term which is used in the ARM ARM.
>
> I am happy for any feedback, especially for the banking of course. It should
> not be too hard to combine these changes with the recent effort towards EL3
> in A64. 
>
> Thanks,
> Fabian
>
> Fabian Aggeler (12):
>   target-arm: add arm_is_secure() function
>   target-arm: add NSACR support
>   target-arm: Split TLB for secure state and EL3 in Aarch64
>   target-arm: add banked coprocessor register type and macros
>   target-arm: Restrict EL3 to Aarch32 state
>   target-arm: Use arm_current_sctlr to access SCTLR
>   target-arm: Use raw_write/raw_read whenever possible
>   target-arm: Convert banked coprocessor registers
>   target-arm: maintain common bits of banked CP registers
>   target-arm: add MVBAR support
>   target-arm: implement IRQ/FIQ routing to Monitor mode
>   target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI
>
> Sergey Fedorov (8):
>   target-arm: move SCR into Security Extensions register list
>   target-arm: adjust TTBCR for Security Extension feature
>   target-arm: reject switching to monitor mode from non-secure state
>   target-arm: adjust arm_current_pl() for Security Extensions
>   target-arm: add non-secure Translation Block flag
>   target-arm: implement CPACR register logic
>   target-arm: add SDER definition
>   target-arm: implement SMC instruction
>
> Svetlana Fedoseeva (3):
>   target-arm: add new CPU feature for Security Extensions
>   target-arm: preserve RAO/WI bits of ARMv7 SCTLR
>   target-arm: add CPU Monitor mode
>
>  hw/arm/pxa2xx.c            |   2 +-
>  linux-user/main.c          |   2 +-
>  target-arm/cpu-qom.h       |   1 +
>  target-arm/cpu.c           |   8 +-
>  target-arm/cpu.h           | 271 ++++++++++++++++++++++---
>  target-arm/helper-a64.c    |   3 +-
>  target-arm/helper.c        | 489 
> ++++++++++++++++++++++++++++++++++++---------
>  target-arm/machine.c       |   6 +-
>  target-arm/op_helper.c     |   2 +-
>  target-arm/translate-a64.c |   9 +-
>  target-arm/translate.c     | 342 ++++++++++++++++++-------------
>  target-arm/translate.h     |   4 +
>  12 files changed, 866 insertions(+), 273 deletions(-)
>