Re: [Qemu-devel] [PATCH RESEND v4 17/18] target-i386: block migration and savevm if invariant tsc is exposed

[Marcelo Tosatti]

On Thu, May 15, 2014 at 02:17:11PM +0200, Juan Quintela wrote:
> Eduardo Habkost <address@hidden> wrote:
> > From: Marcelo Tosatti <address@hidden>
> >
> > Invariant TSC documentation mentions that "invariant TSC will run at a
> > constant rate in all ACPI P-, C-. and T-states".
> >
> > This is not the case if migration to a host with different TSC frequency
> > is allowed, or if savevm is performed. So block migration/savevm.
> >
> > Cc: Juan Quintela <address@hidden>
> > Signed-off-by: Marcelo Tosatti <address@hidden>
> > Reviewed-by: Eduardo Habkost <address@hidden>
> > Signed-off-by: Eduardo Habkost <address@hidden>
> 
> Reviewed-by: Juan Quintela <address@hidden>
> 
> I don't have a better suggestion.  Really we could allow migration to
> identical machines, but I assume that there is not a way to read the tsc
> frequency?
> (Althought reading the model name/numbers could be enough?)

Even if migration to identical machine is performed, you would have 
to perform timing of downtime to compensate.

> I.e. Add a subsection that includes the cpu model name, or whatever we
> can have to identify the host cpu?

"On processors with invariant TSC support, the OS may use the TSC for
wall clock timer services (instead of ACPI or HPET timers)."