Re: [Qemu-devel] [PATCH v3 09/22] target-arm: A64: Introduce aarch64_banked_spsr_index()

[Peter Maydell]

On 19 May 2014 10:22, Edgar E. Iglesias <address@hidden> wrote:
> From: "Edgar E. Iglesias" <address@hidden>
>
> Add aarch64_banked_spsr_index(), used to map an Exception Level
> to an index in the banked_spsr array.
>
> diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> index f120b02..c05a839 100644
> --- a/target-arm/op_helper.c
> +++ b/target-arm/op_helper.c
> @@ -386,7 +386,8 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, 
> uint32_t imm)
>
>  void HELPER(exception_return)(CPUARMState *env)
>  {
> -    uint32_t spsr = env->banked_spsr[0];
> +    unsigned int spsr_idx = is_a64(env) ? aarch64_banked_spsr_index(1) : 0;

This is unnecessary -- if we get here we must have is_a64(env) true,
because this is the helper for an A64 instruction.

> +    uint32_t spsr = env->banked_spsr[spsr_idx];
>      int new_el, i;
>
>      if (env->pstate & PSTATE_SP) {

thanks
-- PMM