Re: [Qemu-devel] [PATCH v3 16/22] target-arm: A64: Generalize ERET to various ELs

[Edgar E. Iglesias]

On Wed, May 21, 2014 at 08:10:53PM +0100, Peter Maydell wrote:
> On 19 May 2014 10:22, Edgar E. Iglesias <address@hidden> wrote:
> > From: "Edgar E. Iglesias" <address@hidden>
> >
> > Adds support for ERET to Aarch64 EL2 and 3.
> >
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> > ---
> >  target-arm/op_helper.c | 10 +++++-----
> >  1 file changed, 5 insertions(+), 5 deletions(-)
> >
> > diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
> > index d89755a..c632dd6 100644
> > --- a/target-arm/op_helper.c
> > +++ b/target-arm/op_helper.c
> > @@ -386,13 +386,13 @@ void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t 
> > op, uint32_t imm)
> >
> >  void HELPER(exception_return)(CPUARMState *env)
> >  {
> > -    unsigned int spsr_idx = is_a64(env) ? aarch64_banked_spsr_index(1) : 0;
> > +    int cur_el = arm_current_pl(env);
> > +    unsigned int spsr_idx = is_a64(env) ? 
> > aarch64_banked_spsr_index(cur_el) : 0;
> 
> This will now allow the guest to trigger an assert() by doing an
> ERET in EL0... The fix for that is to put in the check in translate-a64.c,
> I think, since ERET in EL0 should be an UnallocatedEncoding.

Nice catch. I've prepended this patch with a patch traping eret in el0 at
translation time.

Thanks,
Edgar