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Re: [Qemu-devel] [PATCH v3 16/22] target-arm: A64: Generalize ERET to va
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH v3 16/22] target-arm: A64: Generalize ERET to various ELs |
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Date: |
Thu, 22 May 2014 08:22:35 +0100 |
On 22 May 2014 01:48, Edgar E. Iglesias <address@hidden> wrote:
> On Wed, May 21, 2014 at 08:20:20PM +0100, Peter Maydell wrote:
>> it needs to also fix the bit in the "returning to an exception
>> level which is 32 bit" which says "new_el = 0" since that's
>> not guaranteed to be true any more. (Also I think the register
>> mapping for AArch32 EL2/EL1 needs handling correctly.)
>
> I've tried to stay away from touching too much of the AArch32
> code as I haven't had a setup to test 64/32 transitions
> beyond a64/el1 and a32/el0.
OK; if we put in a TODO comment that we assume EL1..EL3
are 64 bit currently, we'll have a marker to come back and fix
later.
thanks
-- PMM
- [Qemu-devel] [PATCH v3 13/22] target-arm: Register EL3 versions of ELR and SPSR, (continued)
- [Qemu-devel] [PATCH v3 17/22] target-arm: A64: Generalize update_spsel for the various ELs, Edgar E. Iglesias, 2014/05/19
- [Qemu-devel] [PATCH v3 18/22] target-arm: Make vbar_write writeback to any CPREG, Edgar E. Iglesias, 2014/05/19
- [Qemu-devel] [PATCH v3 19/22] target-arm: A64: Register VBAR_EL2, Edgar E. Iglesias, 2014/05/19
- [Qemu-devel] [PATCH v3 20/22] target-arm: A64: Register VBAR_EL3, Edgar E. Iglesias, 2014/05/19
- [Qemu-devel] [PATCH v3 21/22] RFC: target-arm: A32: Use get_mem_index for load/stores, Edgar E. Iglesias, 2014/05/19