Re: [Qemu-devel] target-sparc has inverse cwp logic for SAVE/RESTORE?

[Blue Swirl]

On Mon, May 19, 2014 at 1:56 PM, Mark Cave-Ayland
<address@hidden> wrote:
> On 18/05/14 17:06, Olivier Danet wrote:
>
>> The problem may be related to the fact that the 32bits SPARCv8 and 64bits
>> SPARCv9 work in opposite directions !
>>
>> SparcV9 standard, page 360/399 :
>> The SPARC-V9 CWP register is incremented during a SAVE instruction and
>> decremented during
>> a RESTORE instruction. Although this is the opposite of PSR.CWP’s behavior
>> in SPARC-V8, the
>> only software it should affect is a few trap handlers that operate in
>> privileged mode, and that must
>> be rewritten for SPARC-V9 anyway. This change will have no effect on
>> nonprivileged software.
>
>
> Ah I wonder if that could be it? I did try swapping the increment/decrement
> operators around in the helpers, however OpenBIOS crashed fairly early on so
> it's obviously not as simple as that. I suspect that because a lot of the
> code is shared been v8/v9 then there are some other assumptions that would
> need to be corrected for this to work :/

Yes, QEMU uses v8 register window layout internally also for v9, guest
only sees fixed up CWP. IIRC using v9 layout internally would mean
adjusting a lot of places for marginal performance gains.
Alternatively v9 layout could be used, fixing up CWP for v8.