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[Qemu-devel] [PULL 13/24] tcg-mips: Name the opcode enumeration
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 13/24] tcg-mips: Name the opcode enumeration |
Date: |
Sat, 24 May 2014 08:53:50 -0700 |
And use it in the opcode emission functions.
Reviewed-by: Paolo Bonzini <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/mips/tcg-target.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 54571fb..920208a 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -249,7 +249,7 @@ static inline int tcg_target_const_match(tcg_target_long
val, TCGType type,
}
/* instruction opcodes */
-enum {
+typedef enum {
OPC_J = 0x02 << 26,
OPC_JAL = 0x03 << 26,
OPC_BEQ = 0x04 << 26,
@@ -314,12 +314,12 @@ enum {
OPC_WSBH = OPC_SPECIAL3 | 0x0a0,
OPC_SEB = OPC_SPECIAL3 | 0x420,
OPC_SEH = OPC_SPECIAL3 | 0x620,
-};
+} MIPSInsn;
/*
* Type reg
*/
-static inline void tcg_out_opc_reg(TCGContext *s, int opc,
+static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc,
TCGReg rd, TCGReg rs, TCGReg rt)
{
int32_t inst;
@@ -334,7 +334,7 @@ static inline void tcg_out_opc_reg(TCGContext *s, int opc,
/*
* Type immediate
*/
-static inline void tcg_out_opc_imm(TCGContext *s, int opc,
+static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc,
TCGReg rt, TCGReg rs, TCGArg imm)
{
int32_t inst;
@@ -349,7 +349,7 @@ static inline void tcg_out_opc_imm(TCGContext *s, int opc,
/*
* Type bitfield
*/
-static inline void tcg_out_opc_bf(TCGContext *s, int opc, TCGReg rt,
+static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt,
TCGReg rs, int msb, int lsb)
{
int32_t inst;
@@ -365,7 +365,7 @@ static inline void tcg_out_opc_bf(TCGContext *s, int opc,
TCGReg rt,
/*
* Type branch
*/
-static inline void tcg_out_opc_br(TCGContext *s, int opc,
+static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc,
TCGReg rt, TCGReg rs)
{
/* We pay attention here to not modify the branch target by reading
@@ -379,7 +379,7 @@ static inline void tcg_out_opc_br(TCGContext *s, int opc,
/*
* Type sa
*/
-static inline void tcg_out_opc_sa(TCGContext *s, int opc,
+static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc,
TCGReg rd, TCGReg rt, TCGArg sa)
{
int32_t inst;
@@ -396,7 +396,7 @@ static inline void tcg_out_opc_sa(TCGContext *s, int opc,
* Type jump.
* Returns true if the branch was in range and the insn was emitted.
*/
-static bool tcg_out_opc_jmp(TCGContext *s, int opc, void *target)
+static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, void *target)
{
uintptr_t dest = (uintptr_t)target;
uintptr_t from = (uintptr_t)s->code_ptr + 4;
@@ -525,7 +525,7 @@ static inline void tcg_out_ext16s(TCGContext *s, TCGReg
ret, TCGReg arg)
}
}
-static void tcg_out_ldst(TCGContext *s, int opc, TCGReg data,
+static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data,
TCGReg addr, intptr_t ofs)
{
int16_t lo = ofs;
--
1.9.0
- [Qemu-devel] [PULL 02/24] tcg-mips: Constrain the code_gen_buffer to be within one 256mb segment, (continued)
- [Qemu-devel] [PULL 02/24] tcg-mips: Constrain the code_gen_buffer to be within one 256mb segment, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 04/24] tcg-mips: Fill the exit_tb delay slot, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 05/24] tcg-mips: Split large ldst offsets, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 06/24] tcg-mips: Move softmmu slow path out of line, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 07/24] tcg-mips: Convert to new qemu_l/st helpers, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 08/24] tcg-mips: Convert to new_ldst, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 09/24] tcg-mips: Rearrange register allocation, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 10/24] tcg-mips: Introduce TCG_TMP0, TCG_TMP1, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 11/24] tcg-mips: Use T9 for TCG_TMP1, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 12/24] tcg-mips: Use EXT for AND on mips32r2, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 13/24] tcg-mips: Name the opcode enumeration,
Richard Henderson <=
- [Qemu-devel] [PULL 14/24] tcg-mips: Fix subtract immediate range, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 15/24] tcg-mips: Hoist args loads, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 16/24] tcg-mips: Improve add2/sub2, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 17/24] tcg-mips: Commonize opcode implementations, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 18/24] tcg-mips: Simplify setcond, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 19/24] tcg-mips: Simplify brcond, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 20/24] tcg-mips: Simplify setcond2, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 21/24] tcg-mips: Improve setcond eq/ne vs zeros, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 22/24] tcg-mips: Simplify brcond2, Richard Henderson, 2014/05/24
- [Qemu-devel] [PULL 23/24] tcg-mips: Simplify movcond, Richard Henderson, 2014/05/24