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[Qemu-devel] [PULL 12/26] target-arm: A64: Add SP entries for EL2 and 3
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/26] target-arm: A64: Add SP entries for EL2 and 3 |
Date: |
Tue, 27 May 2014 17:28:20 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/machine.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 62d85ff..ba1d495 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -163,7 +163,7 @@ typedef struct CPUARMState {
uint64_t daif; /* exception masks, in the bits they are in in PSTATE */
uint64_t elr_el[2]; /* AArch64 exception link regs */
- uint64_t sp_el[2]; /* AArch64 banked stack pointers */
+ uint64_t sp_el[4]; /* AArch64 banked stack pointers */
/* System control coprocessor (cp15) */
struct {
diff --git a/target-arm/machine.c b/target-arm/machine.c
index b0fa46d..7b18a90 100644
--- a/target-arm/machine.c
+++ b/target-arm/machine.c
@@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_arm_cpu = {
.name = "cpu",
- .version_id = 17,
- .minimum_version_id = 17,
+ .version_id = 18,
+ .minimum_version_id = 18,
.pre_save = cpu_pre_save,
.post_load = cpu_post_load,
.fields = (VMStateField[]) {
@@ -239,7 +239,7 @@ const VMStateDescription vmstate_arm_cpu = {
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),
VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5),
VMSTATE_UINT64(env.elr_el[1], ARMCPU),
- VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 2),
+ VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4),
/* The length-check must come before the arrays to avoid
* incoming data possibly overflowing the array.
*/
--
1.9.2
- [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 01/26] MAINTAINERS: update Calxeda Highbank maintainer and status, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 12/26] target-arm: A64: Add SP entries for EL2 and 3,
Peter Maydell <=
- [Qemu-devel] [PULL 11/26] target-arm: c12_vbar -> vbar_el[], Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 26/26] target-arm: A64: Register VBAR_EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 10/26] target-arm: Make esr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 24/26] target-arm: Make vbar_write writeback to any CPREG, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 21/26] target-arm: A64: Trap ERET from EL0 at translation time, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 17/26] target-arm: Add a feature flag for EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 18/26] target-arm: Register EL2 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27