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[Qemu-devel] [PULL 26/26] target-arm: A64: Register VBAR_EL3
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 26/26] target-arm: A64: Register VBAR_EL3 |
Date: |
Tue, 27 May 2014 17:28:34 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 2 +-
target-arm/helper.c | 5 +++++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3ccbd95..8d04385 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -198,7 +198,7 @@ typedef struct CPUARMState {
uint32_t c9_pmuserenr; /* perf monitor user enable */
uint32_t c9_pminten; /* perf monitor interrupt enables */
uint64_t mair_el1;
- uint64_t vbar_el[3]; /* vector base address register */
+ uint64_t vbar_el[4]; /* vector base address register */
uint32_t c13_fcse; /* FCSE PID. */
uint64_t contextidr_el1; /* Context ID. */
uint64_t tpidr_el0; /* User RW Thread register. */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index c769ef2..6a01c6a 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -2138,6 +2138,11 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
.type = ARM_CP_NO_MIGRATE,
.opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
+ { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
+ .access = PL3_RW, .writefn = vbar_write,
+ .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
+ .resetvalue = 0 },
REGINFO_SENTINEL
};
--
1.9.2
- [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 01/26] MAINTAINERS: update Calxeda Highbank maintainer and status, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 12/26] target-arm: A64: Add SP entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 11/26] target-arm: c12_vbar -> vbar_el[], Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 26/26] target-arm: A64: Register VBAR_EL3,
Peter Maydell <=
- [Qemu-devel] [PULL 10/26] target-arm: Make esr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 24/26] target-arm: Make vbar_write writeback to any CPREG, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 22/26] target-arm: A64: Generalize ERET to various ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 21/26] target-arm: A64: Trap ERET from EL0 at translation time, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 17/26] target-arm: Add a feature flag for EL3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 18/26] target-arm: Register EL2 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 19/26] target-arm: Register EL3 versions of ELR and SPSR, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 16/26] target-arm: Add a feature flag for EL2, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 15/26] target-arm: A64: Introduce aarch64_banked_spsr_index(), Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 23/26] target-arm: A64: Generalize update_spsel for the various ELs, Peter Maydell, 2014/05/27