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[Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h |
Date: |
Tue, 27 May 2014 17:28:12 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
So that it can be shared with the AArch32 code.
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/translate-a64.c | 9 ---------
target-arm/translate.h | 9 +++++++++
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index b62db4d..bfd139a 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -162,15 +162,6 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f,
}
}
-static int get_mem_index(DisasContext *s)
-{
-#ifdef CONFIG_USER_ONLY
- return 1;
-#else
- return s->user;
-#endif
-}
-
void gen_a64_set_pc_im(uint64_t val)
{
tcg_gen_movi_i64(cpu_pc, val);
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 34328f4..8737af0 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -52,6 +52,15 @@ static inline int arm_dc_feature(DisasContext *dc, int
feature)
return (dc->features & (1ULL << feature)) != 0;
}
+static inline int get_mem_index(DisasContext *s)
+{
+#ifdef CONFIG_USER_ONLY
+ return 1;
+#else
+ return s->user;
+#endif
+}
+
/* target-specific extra values for is_jmp */
/* These instructions trap after executing, so the A32/T32 decoder must
* defer them until after the conditional execution state has been updated.
--
1.9.2
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, (continued)
- [Qemu-devel] [PULL 14/26] target-arm: Add SPSR entries for EL2/HYP and EL3/MON, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 08/26] target-arm: Use a 1:1 mapping between EL and MMU index, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 13/26] target-arm: A64: Add ELR entries for EL2 and 3, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 20/26] target-arm: A64: Forbid ERET to higher or unimplemented ELs, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 05/26] target-arm/translate.c: Clean up mmu index handling for ldrt/strt, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 06/26] target-arm/translate.c: Use get_mem_index() for SRS memory accesses, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 02/26] hw/display/pxa2xx_lcd: Fix 16bpp+alpha and 18bpp+alpha palette formats, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 07/26] target-arm: A32: Use get_mem_index for load/stores, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 09/26] target-arm: Make elr_el1 an array, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 03/26] target-arm: implement CPACR register logic for ARMv7, Peter Maydell, 2014/05/27
- [Qemu-devel] [PULL 04/26] target-arm: Move get_mem_index to translate.h,
Peter Maydell <=
- Re: [Qemu-devel] [PULL 00/26] target-arm queue, Peter Maydell, 2014/05/28