At the moment every POWER CPU family has its own init_proc_POWERX
function.
E500 already has common init function so we try to do the same thing.
This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+.
This introduces generalized init_proc_POWER() which accepts a CPU type
as a parameter.
This uses new init function for 970 and POWER5+ CPU classes.
970 and POWER5+ use the same CPU class initialization except 3 things:
1. logical partitioning is controlled by LPCR (POWER5+) and HID4 (970)
SPRs;
2. 970 does not have EAR (External Access Register) SPR and PowerISA 2.03
defines one so keep it only for POWER5+;
3. POWER5+ does not have ALTIVEC so insns_flags does not have PPC_ALTIVEC
flag set and gen_spr_book3s_altivec() won't init ALTIVEC for POWER5+.
Signed-off-by: Alexey Kardashevskiy <address@hidden>
---
target-ppc/translate_init.c | 85
++++++++++++++-------------------------------
1 file changed, 27 insertions(+), 58 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 7662730..5556b02 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7273,6 +7273,11 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
#define POWERPC970_HID5_INIT 0x00000000
#endif
+enum BOOK3S_CPU_TYPE {
+ BOOK3S_CPU_970,
+ BOOK3S_CPU_POWER5PLUS,
+};
+
static int check_pow_970 (CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x01C00000) {
@@ -7474,6 +7479,15 @@ static void
gen_spr_book3s_external_control(CPUPPCState *env)
0x00000000);
}
+static void gen_spr_book3s_lpar(CPUPPCState *env)
+{
+ /* Logical partitionning */
+ spr_register_kvm(env, SPR_LPCR, "LPCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_LPCR, 0x00000000);
+}
+
static void gen_spr_970_lpar(CPUPPCState *env)
{
/* Logical partitionning */
@@ -7484,7 +7498,7 @@ static void gen_spr_970_lpar(CPUPPCState *env)
0x00000000);
}
-static void init_proc_970 (CPUPPCState *env)
+static void init_proc_POWER(CPUPPCState *env, int version)