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[Qemu-devel] [PATCH v1 15/16] target-arm: Add IRQ and FIQ routing to EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v1 15/16] target-arm: Add IRQ and FIQ routing to EL2 and 3 |
Date: |
Fri, 30 May 2014 17:28:30 +1000 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 10 ++++++++++
target-arm/helper.c | 16 ++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index b3631f2..d15e8d2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1133,6 +1133,8 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
CPUARMState *env = cs->env_ptr;
unsigned int cur_el = arm_current_pl(env);
unsigned int target_el = arm_excp_target_el(cs, excp_idx);
+ /* FIXME: Use actual secure state. */
+ bool secure = false;
/* Don't take exceptions if they target a lower EL. */
if (cur_el > target_el) {
@@ -1141,8 +1143,16 @@ static inline bool arm_excp_unmasked(CPUState *cs,
unsigned int excp_idx)
switch (excp_idx) {
case EXCP_FIQ:
+ if (!secure && cur_el < 2 && target_el == 2
+ && (env->cp15.hcr_el2 & HCR_FMO)) {
+ return true;
+ }
return !(env->daif & PSTATE_F);
case EXCP_IRQ:
+ if (!secure && cur_el < 2 && target_el == 2
+ && (env->cp15.hcr_el2 & HCR_IMO)) {
+ return true;
+ }
return ((IS_M(env) && env->regs[15] < 0xfffffff0)
|| !(env->daif & PSTATE_I));
default:
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 35091ea..649476b 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3304,6 +3304,22 @@ unsigned int arm_excp_target_el(CPUState *cs, unsigned
int excp_idx)
target_el = 2;
}
break;
+ case EXCP_IRQ:
+ if (!secure && (env->cp15.hcr_el2 & HCR_IMO)) {
+ target_el = 2;
+ }
+ if (env->cp15.scr_el3 & SCR_IRQ) {
+ target_el = 3;
+ }
+ break;
+ case EXCP_FIQ:
+ if (!secure && (env->cp15.hcr_el2 & HCR_FMO)) {
+ target_el = 2;
+ }
+ if (env->cp15.scr_el3 & SCR_FIQ) {
+ target_el = 3;
+ }
+ break;
}
return target_el;
}
--
1.8.3.2
- [Qemu-devel] [PATCH v1 07/16] target-arm: Add HCR_EL2, (continued)
- [Qemu-devel] [PATCH v1 07/16] target-arm: Add HCR_EL2, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 08/16] target-arm: Add SCR_EL3, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 09/16] target-arm: A64: Refactor aarch64_cpu_do_interrupt, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 10/16] target-arm: Break out exception masking to a separate func, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 11/16] target-arm: Don't take interrupts targeting lower ELs, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 12/16] target-arm: A64: Correct updates to FAR and ESR on exceptions, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 13/16] target-arm: A64: Emulate the HVC insn, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 14/16] target-arm: A64: Emulate the SMC insn, Edgar E. Iglesias, 2014/05/30
- [Qemu-devel] [PATCH v1 15/16] target-arm: Add IRQ and FIQ routing to EL2 and 3,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v1 16/16] target-arm: Add support for VIRQ and VFIQ, Edgar E. Iglesias, 2014/05/30