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[Qemu-devel] [PATCH 4/9] target-arm: VFPv4 implies half-precision extens
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 4/9] target-arm: VFPv4 implies half-precision extension |
Date: |
Fri, 30 May 2014 14:55:20 +0100 |
VFPv4 implies the presence of the half-precision floating point
extension (which is optional in VFPv3). Add this implied rule
to arm_cpu_realizefn() and remove some no-longer-needed explicit
setting of the bit in initfns.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.c | 3 +--
target-arm/cpu64.c | 2 --
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index bc19d80..b877835 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -348,6 +348,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error
**errp)
}
if (arm_feature(env, ARM_FEATURE_VFP4)) {
set_feature(env, ARM_FEATURE_VFP3);
+ set_feature(env, ARM_FEATURE_VFP_FP16);
}
if (arm_feature(env, ARM_FEATURE_VFP3)) {
set_feature(env, ARM_FEATURE_VFP);
@@ -744,7 +745,6 @@ static void cortex_a15_initfn(Object *obj)
cpu->dtb_compatible = "arm,cortex-a15";
set_feature(&cpu->env, ARM_FEATURE_V7);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
- set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
@@ -953,7 +953,6 @@ static void arm_any_initfn(Object *obj)
ARMCPU *cpu = ARM_CPU(obj);
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
- set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
set_feature(&cpu->env, ARM_FEATURE_V8_AES);
diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
index 0e89265..74abd3c 100644
--- a/target-arm/cpu64.c
+++ b/target-arm/cpu64.c
@@ -93,7 +93,6 @@ static void aarch64_a57_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
- set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
@@ -142,7 +141,6 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8);
set_feature(&cpu->env, ARM_FEATURE_VFP4);
- set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
set_feature(&cpu->env, ARM_FEATURE_NEON);
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
set_feature(&cpu->env, ARM_FEATURE_V8_AES);
--
1.9.2
- [Qemu-devel] [PATCH 0/9] target-arm: A64: Implement crypto insns, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 4/9] target-arm: VFPv4 implies half-precision extension,
Peter Maydell <=
- [Qemu-devel] [PATCH 2/9] target-arm: Remove unnecessary setting of feature bits, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 1/9] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 9/9] target-arm: A64: Implement two-register SHA instructions, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 3/9] target-arm: Clean up handling of ARMv8 optional feature bits, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 8/9] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 6/9] target-arm: A32/T32: Mask CRC value in calling code, not helper, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 5/9] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/05/30
- [Qemu-devel] [PATCH 7/9] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/05/30