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[Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMU
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL |
Date: |
Mon, 9 Jun 2014 15:57:27 +0100 |
Now that we have a separate ARM_FEATURE_V8_PMULL bit, use it for
the A64 PMULL, not the AES feature bit.
Signed-off-by: Peter Maydell <address@hidden>
---
linux-user/elfload.c | 2 +-
target-arm/translate-a64.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 3241fec..e872493 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -539,7 +539,7 @@ static uint32_t get_elf_hwcap(void)
/* probe for the extra features */
#define GET_FEATURE(feat, hwcap) \
do { if (arm_feature(&cpu->env, feat)) { hwcaps |= hwcap; } } while (0)
- GET_FEATURE(ARM_FEATURE_V8_AES, ARM_HWCAP_A64_PMULL);
+ GET_FEATURE(ARM_FEATURE_V8_PMULL, ARM_HWCAP_A64_PMULL);
#undef GET_FEATURE
return hwcaps;
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index a9c4633..9832cc3 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8574,7 +8574,7 @@ static void disas_simd_three_reg_diff(DisasContext *s,
uint32_t insn)
return;
}
if (size == 3) {
- if (!arm_dc_feature(s, ARM_FEATURE_V8_AES)) {
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_PMULL)) {
unallocated_encoding(s);
return;
}
--
1.9.2
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 20/20] target-arm: Delete unused iwmmxt_msadb helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 18/20] target-arm: A64: Implement two-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 19/20] target-arm: Fix errors in writes to generic timer control registers, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 15/20] target-arm: A32/T32: Mask CRC value in calling code, not helper, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 16/20] target-arm: A64: Implement AES instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 13/20] target-arm: VFPv4 implies half-precision extension, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 14/20] target-arm: A64: Implement CRC instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 11/20] target-arm: Remove unnecessary setting of feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 09/20] target-arm: A64: Use PMULL feature bit for PMULL,
Peter Maydell <=
- [Qemu-devel] [PULL 10/20] target-arm: arm_any_initfn() should never set ARM_FEATURE_AARCH64, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 07/20] target-arm: Allow 3reg_wide undefreq to encode more bad size options, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 08/20] target-arm: add support for v8 VMULL.P64 instruction, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 17/20] target-arm: A64: Implement 3-register SHA instructions, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 05/20] target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 12/20] target-arm: Clean up handling of ARMv8 optional feature bits, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 02/20] target-arm/cpu64.c: Actually register Cortex-A57 impdef registers, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 04/20] target-arm: implement PD0/PD1 bits for TTBCR, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 01/20] vexpress: Add support for the -bios flag to provide firmware, Peter Maydell, 2014/06/09
- [Qemu-devel] [PULL 06/20] target-arm: add support for v8 SHA1 and SHA256 instructions, Peter Maydell, 2014/06/09