Re: [Qemu-devel] [PATCH v2 12/22] target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructions

[Richard Henderson]

On 06/11/2014 08:19 AM, Leon Alrae wrote:
> * add missing zero register case

What missing zero register case?

> +        if (rd == 0) {
> +            /* Treat as NOP. */
> +            break;
> +        }

This is normally handled by gen_store_gpr...

> +            if (rt == 0) {
> +                tcg_gen_movi_tl(cpu_gpr[rd], 0);
> +            } else {
> +                gen_helper_dbitswap(cpu_gpr[rd], cpu_gpr[rt]);
> +            }
> +            break;

... and this is normally handed by gen_load_gpr.

Open-coding these tests just clutters the code, making it harder to read.  C.f.
the 1500 lines removed during a cleanup of target-alpha for exactly this sort
of thing.


r~