Re: [Qemu-devel] [PATCH v3 31/32] target-arm: make VBAR banked

[Greg Bellows]

On 10 June 2014 18:55, Fabian Aggeler <address@hidden> wrote:

When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.

Signed-off-by: Fabian Aggeler <address@hidden>
---
 target-arm/cpu.h        | 12 +++++++++++-
 target-arm/helper-a64.c |  6 +++++-
 target-arm/helper.c     | 14 +++++++-------
 3 files changed, 23 insertions(+), 9 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 048ede9..c7d606e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -317,7 +317,17 @@ typedef struct CPUARMState {
         uint32_t c9_pmuserenr; /* perf monitor user enable */
         uint32_t c9_pminten; /* perf monitor interrupt enables */
         uint64_t mair_el1;
-        uint64_t vbar_el[4]; /* vector base address register */
+        struct { /* vector base address register */
+            union {
+                uint64_t vbar_ns;
+                uint64_t vbar_s;
+            };
+            union {
+                uint64_t vbar_el1;
+                uint64_t vbar_el3;
+            };
+        };
+        uint64_t vbar_el2;

This is broken.  I think the intent is a union of 2 structs rather than a struct of two unions.  Plus, vbar_el2 should be added in and hvbar made a union of it.

union {

    struct {

        uint64_t vbar_ns;

        uint64_t hvbar;

        uint64_t vbar_s;

    };

    struct {

        uint64_t vbar_el1;

        uint64_t vbar_el2;

        uint64_t vbar_el3;

    };

}; 

         uint64_t mvbar; /* (monitor) vector base address register */
         uint32_t c13_fcse; /* FCSE PID.  */
         uint64_t contextidr_el1; /* Context ID.  */
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 1fc0d3c..a66ec94 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -444,19 +444,23 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
     ARMCPU *cpu = ARM_CPU(cs);
     CPUARMState *env = &cpu->env;
     unsigned int new_el = arm_excp_target_el(cs, cs->exception_index);
-    target_ulong addr = env->cp15.vbar_el[new_el];
+    target_ulong addr = 0;
     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
     int i;
     uint64_t *target_esr;
+
     switch (new_el) {
     case 3:
         target_esr = &env->cp15.esr_el3;
+        addr = env->cp15.vbar_el3;
         break;
     case 2:
         target_esr = &env->cp15.esr_el2;
+        addr = env->cp15.vbar_el2;
         break;
     case 1:
         target_esr = &env->cp15.esr_el1;
+        addr = env->cp15.vbar_el1;
         break;
     }

diff --git a/target-arm/helper.c b/target-arm/helper.c
index c3195bd..2d085aa 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -803,11 +803,11 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
       .resetvalue = 0, .writefn = pmintenclr_write, },
-    { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
+    { .name = "VBAR_EL1", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
-      .access = PL1_RW, .writefn = vbar_write,
-      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
-      .resetvalue = 0 },
+      .access = PL1_RW, .writefn = vbar_write, .resetvalue = 0,
+      .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
+                             offsetof(CPUARMState, cp15.vbar_ns) } },

In the cases where we are registering banked registers, it may be clearer to keep the v7 name such as VBAR, because a banked VBAR_EL1 is counter intuitive.

 

     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
@@ -2207,7 +2207,7 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
       .access = PL2_RW, .writefn = vbar_write,
-      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
+      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el2),
       .resetvalue = 0 },
     REGINFO_SENTINEL
 };
@@ -2319,7 +2319,7 @@ static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
       .access = PL3_RW, .writefn = vbar_write,
-      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
+      .fieldoffset = offsetof(CPUARMState, cp15.vbar_el3),
       .resetvalue = 0 },
     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
@@ -3910,7 +3910,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
          * This register is only followed in non-monitor mode, and is banked.
          * Note: only bits 31:5 are valid.
          */
-        addr += env->cp15.vbar_el[1];
+        addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
     }

     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
--
1.8.3.2