Re: [Qemu-devel] [PATCH v2 07/17] target-arm: Add HCR_EL2

[Edgar E. Iglesias]

On Wed, Jun 11, 2014 at 10:48:25AM -0500, Greg Bellows wrote:
> On 9 June 2014 10:04, Edgar E. Iglesias <address@hidden> wrote:
> 
> > From: "Edgar E. Iglesias" <address@hidden>
> >
> > Signed-off-by: Edgar E. Iglesias <address@hidden>
> > ---
> >  target-arm/cpu.h    | 35 +++++++++++++++++++++++++++++++++++
> >  target-arm/helper.c | 27 +++++++++++++++++++++++++++
> >  2 files changed, 62 insertions(+)
> >
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index 5114d26..cd8c9a7 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -184,6 +184,7 @@ typedef struct CPUARMState {
> >                          MPU write buffer control.  */
> >          uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */
> >          uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
> > +        uint64_t hcr_el2; /* Hypervisor configuration register */
> >          uint32_t ifsr_el2; /* Fault status registers.  */
> >          uint64_t esr_el[4];
> >          uint32_t c6_region[8]; /* MPU base/size registers.  */
> > @@ -526,6 +527,40 @@ static inline void xpsr_write(CPUARMState *env,
> > uint32_t val, uint32_t mask)
> >      }
> >  }
> >
> > +#define HCR_VM        (1ULL << 0)
> > +#define HCR_SWIO      (1ULL << 1)
> > +#define HCR_PTW       (1ULL << 2)
> > +#define HCR_FMO       (1ULL << 3)
> > +#define HCR_IMO       (1ULL << 4)
> > +#define HCR_AMO       (1ULL << 5)
> > +#define HCR_VF        (1ULL << 6)
> > +#define HCR_VI        (1ULL << 7)
> > +#define HCR_VSE       (1ULL << 8)
> > +#define HCR_FB        (1ULL << 9)
> >
> 
> You went to the trouble to enumerate all the bits but skipped BSU.  For
> consistency should we just add it and the mask?


Will add it in v3.

> 
> 
> > +#define HCR_DC        (1ULL << 12)
> > +#define HCR_TWI       (1ULL << 13)
> > +#define HCR_TWE       (1ULL << 14)
> > +#define HCR_TID0      (1ULL << 15)
> > +#define HCR_TID1      (1ULL << 16)
> > +#define HCR_TID2      (1ULL << 17)
> > +#define HCR_TID3      (1ULL << 18)
> > +#define HCR_TSC       (1ULL << 19)
> > +#define HCR_TIDCP     (1ULL << 20)
> > +#define HCR_TACR      (1ULL << 21)
> > +#define HCR_TSW       (1ULL << 22)
> > +#define HCR_TPC       (1ULL << 23)
> > +#define HCR_TPU       (1ULL << 24)
> > +#define HCR_TTLB      (1ULL << 25)
> > +#define HCR_TVM       (1ULL << 26)
> > +#define HCR_TGE       (1ULL << 27)
> > +#define HCR_TDZ       (1ULL << 28)
> > +#define HCR_HCD       (1ULL << 29)
> > +#define HCR_TRVM      (1ULL << 30)
> > +#define HCR_RW        (1ULL << 31)
> > +#define HCR_CD        (1ULL << 32)
> > +#define HCR_ID        (1ULL << 33)
> > +#define HCR_MASK      ((1ULL << 34) - 1)
> > +
> >  /* Return the current FPSCR value.  */
> >  uint32_t vfp_get_fpscr(CPUARMState *env);
> >  void vfp_set_fpscr(CPUARMState *env, uint32_t val);
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index 90874c4..d28951a 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -2107,10 +2107,37 @@ static const ARMCPRegInfo
> > v8_el3_no_el2_cp_reginfo[] = {
> >        .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
> >        .access = PL2_RW,
> >        .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
> > +    { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
> > +      .type = ARM_CP_NO_MIGRATE,
> > +      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
> > +      .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
> >      REGINFO_SENTINEL
> >  };
> >
> > +static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t
> > value)
> > +{
> > +    ARMCPU *cpu = arm_env_get_cpu(env);
> > +    uint64_t valid_mask = HCR_MASK;
> > +
> > +    if (!arm_feature(env, ARM_FEATURE_EL3)) {
> > +        valid_mask &= ~HCR_HCD;
> > +    }
> > +
> > +    /* Clear RES0 bits.  */
> > +    value &= valid_mask;
> > +
> > +    if ((raw_read(env, ri) ^ value) & HCR_VM) {
> > +        /* Flush the TLB when turning VM on/off.  */
> > +        tlb_flush(CPU(cpu), 1);
> >
> 
> There are a few other bits that can be cached in the TLB (RW, DC), perhaps
> we should check and flush for change to them as well.

Will do in v3

Thanks,
Edgar

> 
> 
> > +    }
> > +    raw_write(env, ri, value);
> > +}
> > +
> >  static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
> > +    { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
> > +      .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
> > +      .access = PL2_RW, .fieldoffset = offsetof(CPUARMState,
> > cp15.hcr_el2),
> > +      .writefn = hcr_write },
> >      { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
> >        .type = ARM_CP_NO_MIGRATE,
> >        .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
> > --
> > 1.8.3.2
> >
> >