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Re: [Qemu-devel] Endian control register


From: Benjamin Herrenschmidt
Subject: Re: [Qemu-devel] Endian control register
Date: Mon, 16 Jun 2014 21:07:41 +1000

On Mon, 2014-06-16 at 11:45 +0100, Peter Maydell wrote:
> On 16 June 2014 11:30, Benjamin Herrenschmidt <address@hidden> wrote:
> > So while trying to solve an issue we have with qemu/kvm and powerpc who
> > can be both LE and BE nowadays, we thought the ideal solution would be
> > to have a register in the emulated VGA to control the endian.
> 
> > Any suggestion ? Comment ? Flame ? :-)
> 
> My instinctive reaction is to ask if this exists in actual
> VGA hardware. If not, then it doesn't really seem like it
> belongs in our VGA device model...

Actual VGA HW try to handle endianness using a range of more or less
broken solutions, so it's hard to compare :-)

A whole range of them historically such as older radeons had "apertures"
with a HW swap on the PCI to VRAM path allowing them internally to
continue using the same pixel format in VRAM. But that has issue, the
swappers must be adjusted for the actual bpp and things get tricky if
several objects in VRAM have different bpp which becomes common with
textures, or even render masks.

nVidia is a bit smarter and I think have the swapper on the units
consuming the pixels, I think they have per "object" endian settings but
I'm not 100% certain.

Recent radeons also have swappers per units which is a lot saner.

What I propose is somewhat equivalent to the two latter, but with only a
single object/unit, which is the framebuffer (since we don't do other
accelerations or drawing).

So yes, it somewhat relates to what is done elsewhere :-)

It is also the best solution we could find to the problem after some
discussion on IRC. The other solution is to try to hook when the guest
does the hypercall (yay paravirtualization !) to switch the endian mode
of interrupts and use it to "adjust" qemu internal vga byteswap but
that's frankly a lot more gross than having the VGA provide a
self-contained endian setting.

Cheers,
Ben.





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