Re: [Qemu-devel] [PATCH v2 18/22] target-mips: do not allow Status.FR=0 mode in 64-bit FPU

[Aurelien Jarno]

On Wed, Jun 11, 2014 at 04:19:48PM +0100, Leon Alrae wrote:
> Status.FR bit must be ignored on write and read as 1 when an implementation of
> Release 6 of the Architecture in which a 64-bit floating point unit is
> implemented.
> 
> Signed-off-by: Leon Alrae <address@hidden>
> ---
>  target-mips/translate.c |    7 +++++++
>  1 files changed, 7 insertions(+), 0 deletions(-)
> 
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index 4c75006..e635999 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -17899,6 +17899,13 @@ void cpu_state_reset(CPUMIPSState *env)
>          }
>      }
>  #endif
> +    if ((env->insn_flags & ISA_MIPS32R6) &&
> +        (env->active_fpu.fcr0 & (1 << FCR0_F64))) {
> +        /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */
> +        env->CP0_Status |= (1 << CP0St_FR);

This is fine

> +        env->CP0_Status_rw_bitmask &= ~(1 << CP0St_FR);

IMHO This should be done directly in the CPU definition.

> +    }
> +
>      compute_hflags(env);
>      cs->exception_index = EXCP_NONE;
>  }
> -- 
> 1.7.5.4
> 
> 

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
address@hidden                 http://www.aurel32.net