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[Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask
From: |
greg . bellows |
Subject: |
[Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked |
Date: |
Mon, 30 Jun 2014 18:09:25 -0500 |
From: Fabian Aggeler <address@hidden>
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler <address@hidden>
Signed-off-by: Greg Bellows <address@hidden>
---
target-arm/cpu.h | 10 ++++++++--
target-arm/helper.c | 15 +++++++++------
2 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 35291a6..367665e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -232,8 +232,14 @@ typedef struct CPUARMState {
uint64_t tcr_el3;
};
};
- uint32_t c2_mask; /* MMU translation table base selection mask. */
- uint32_t c2_base_mask; /* MMU translation table base 0 mask. */
+ struct { /* MMU translation table base selection mask. */
+ uint32_t c2_mask_ns;
+ uint32_t c2_mask_s;
+ };
+ struct { /* MMU translation table base 0 mask. */
+ uint32_t c2_base_mask_ns;
+ uint32_t c2_base_mask_s;
+ };
uint32_t c2_data; /* MPU data cachable bits. */
uint32_t c2_insn; /* MPU instruction cachable bits. */
uint32_t c3; /* MMU domain access control register
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8326d1f..1006b57 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1446,8 +1446,11 @@ static void vmsa_ttbcr_raw_write(CPUARMState *env, const
ARMCPRegInfo *ri,
* and the c2_mask and c2_base_mask values are meaningless.
*/
raw_write(env, ri, value);
- env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
- env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
+
+ A32_BANKED_CURRENT_REG_SET(env, c2_mask,
+ ~(((uint32_t)0xffffffffu) >> maskshift));
+ A32_BANKED_CURRENT_REG_SET(env, c2_base_mask,
+ ~((uint32_t)0x3fffu >> maskshift));
}
static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -1466,9 +1469,9 @@ static void vmsa_ttbcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
{
- env->cp15.c2_base_mask = 0xffffc000u;
+ A32_BANKED_CURRENT_REG_SET(env, c2_base_mask, 0xffffc000u);
raw_write(env, ri, 0);
- env->cp15.c2_mask = 0;
+ A32_BANKED_CURRENT_REG_SET(env, c2_mask, 0);
}
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -4018,7 +4021,7 @@ static bool get_level1_table_address(CPUARMState *env,
uint32_t *table,
* Aarch32 there is a secure and non-secure instance of the translation
* table registers.
*/
- if (address & env->cp15.c2_mask) {
+ if (address & A32_BANKED_CURRENT_REG_GET(env, c2_mask)) {
if (A32_BANKED_CURRENT_REG_GET(env, ttbcr) & TTBCR_PD1) {
/* Translation table walk disabled for TTBR1 */
return false;
@@ -4030,7 +4033,7 @@ static bool get_level1_table_address(CPUARMState *env,
uint32_t *table,
return false;
}
*table = A32_BANKED_CURRENT_REG_GET(env, ttbr0) &
- env->cp15.c2_base_mask;
+ A32_BANKED_CURRENT_REG_GET(env, c2_base_mask);
}
*table |= (address >> 18) & 0x3ffc;
return true;
--
1.8.3.2
- [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register, (continued)
- [Qemu-devel] [PATCH v4 15/33] target-arm: add NSACR register, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 16/33] target-arm: add SDER definition, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 17/33] target-arm: add MVBAR support, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 18/33] target-arm: add macros to access banked registers, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 19/33] target-arm: insert Aarch32 cpregs twice into hashtable, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 20/33] target-arm: arrayfying fieldoffset for banking, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 21/33] target-arm: add SCTLR_EL3 and make SCTLR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 22/33] target-arm: make CSSELR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 23/33] target-arm: add TTBR0_EL3 and make TTBR0/1 banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 24/33] target-arm: add TCR_EL3 and make TTBCR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 25/33] target-arm: make c2_mask and c2_base_mask banked,
greg . bellows <=
- [Qemu-devel] [PATCH v4 26/33] target-arm: make DACR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 27/33] target-arm: make IFSR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 28/33] target-arm: make DFSR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 29/33] target-arm: make IFAR/DFAR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 32/33] target-arm: make c13 cp regs banked (FCSEIDR, ...), greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 33/33] target-arm: Limit migration of duplicate CP regs, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 31/33] target-arm: make VBAR banked, greg . bellows, 2014/06/30
- [Qemu-devel] [PATCH v4 30/33] target-arm: make PAR banked, greg . bellows, 2014/06/30